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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k11-20020a7bc40b000000b0039c5cecf206sm1925079wmi.4.2022.07.14.06.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 06:23:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Idan Horowitz Subject: [PATCH 0/7] target/arm: Handle VTCR_EL2 bits shared between S and NS EL2 Date: Thu, 14 Jul 2022 14:22:56 +0100 Message-Id: <20220714132303.1287193-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In https://gitlab.com/qemu-project/qemu/-/issues/1103 Idan pointed out that our regime_tcr() function doesn't handle the fact that some of the config bits for the Secure stage 2 translation regime are shared with NS EL2 and stored in VTCR_EL2 rather than VSTCR_EL2. Currently the only visible effect of this is that if the guest tries to enable LPA2 via VTCR_EL2.DS QEMU will incorrectly fail to honour this for Secure stage 2 translations. The final patch in this series fixes this, by synthesizing a VTCR_EL2 format value for Secure stage 2 by merging together the shared VTCR_EL2 fields into the VSTCR_EL2 value. The first six patches get rid of a very longstanding micro-optimization of our TCR register handling that gets in the way of fixing the bug. Currently regime_tcr() returns a pointer to a TCR struct, which contains both the 64-bit TCR value and also two 'base_mask' and 'mask' values, which are pre-calculated when the register is written. Those values are used only in the get_level1_table_address() function. That function is called once per page table walk for 32-bit short-descriptor page tables only. The pre-calculation saves only a handful of logical shifting and masking instructions, which is a tiny amount of overhead compared to everything else we need to do on a guest page table walk. Conversely the microoptimization adds extra complexity on TCR register writes, and code complexity handling the TCR struct. It therefore no longer seems to be pulling its weight, and we're better off without it, rather than jumping through hoops to come up with a fix to the VSTCR_EL2 issue that lets us retain it. thanks -- PMM Peter Maydell (7): target/arm: Define and use new regime_tcr_value() function target/arm: Calculate mask/base_mask in get_level1_table_address() target/arm: Fold regime_tcr() and regime_tcr_value() together target/arm: Fix big-endian host handling of VTCR target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t target/arm: Store TCR_EL* registers as uint64_t target/arm: Honour VTCR_EL2 bits in Secure EL2 target/arm/cpu.h | 31 ++++++++++---- target/arm/internals.h | 34 +++++++++++---- target/arm/cpu.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/helper.c | 87 +++++++++++---------------------------- target/arm/ptw.c | 38 +++++++++-------- target/arm/tlb_helper.c | 2 +- 7 files changed, 96 insertions(+), 100 deletions(-)