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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id y3-20020a17090a390300b001ef81bac701sm1782089pjb.42.2022.07.08.08.47.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:47:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [RISU PATCH v4 00/29] risu cleanups and improvements Date: Fri, 8 Jul 2022 21:16:31 +0530 Message-Id: <20220708154700.18682-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If you can imagine, v3 was back in 2020: https://lore.kernel.org/qemu-devel/20200522023440.26261-1-richard.henderson@linaro.org/ I've refreshed that, not that risu has changed much in that time, and then also added support for SME to aarch64, i.e. SVCR and ZA storage are now present in the reginfo, and compared. I include a small test case, which allows one to see that ZA storage is being handled properly. When run with ./risu --test-sve=1 --test-za=1 --master -t test_sme_aarch64.{out,bin} ./risu --fulldump -t test_sme_aarch64.out one can see the 16x16 bytes filled with row major then column major indexes. r~ Richard Henderson (29): Use bool for tracing variables Unify master_fd and apprentice_fd to comm_fd Hoist trace file and socket opening Adjust tracefile open for write Use EXIT_FAILURE, EXIT_SUCCESS Make some risu.c symbols static Add enum RisuOp Add enum RisuResult Unify i/o functions and use RisuResult Pass non-OK result back through siglongjmp Always write for --master Simplify syncing with master Split RES_MISMATCH for registers and memory Merge reginfo.c into risu.c Rearrange reginfo and memblock buffers Split out recv_register_info Add magic and size to the trace header Compute reginfo_size based on the reginfo aarch64: Assume system support for SVE aarch64: Reorg sve reginfo to save space aarch64: Use arch_init to configure sve ppc64: Use uint64_t to represent double Standardize reginfo_dump_mismatch printing Add --fulldump and --diffdup options Remove return value from reginfo_dump ppc64: Clean up reginfo handling aarch64: Tidy reginfo dumping ahead of ZA state aarch64: Add support for ZA storage aarch64: Trivial SME test Makefile | 2 +- risu.h | 103 +++---- risu_reginfo_aarch64.h | 97 ++++-- risu_reginfo_ppc64.h | 3 +- comms.c | 34 +-- reginfo.c | 183 ----------- risu.c | 676 ++++++++++++++++++++++++++++++----------- risu_aarch64.c | 6 +- risu_arm.c | 6 +- risu_i386.c | 4 +- risu_m68k.c | 4 +- risu_ppc64.c | 4 +- risu_reginfo_aarch64.c | 408 +++++++++++++++---------- risu_reginfo_arm.c | 32 +- risu_reginfo_i386.c | 22 +- risu_reginfo_m68k.c | 37 +-- risu_reginfo_ppc64.c | 183 +++++------ test_sme_aarch64.s | 55 ++++ 18 files changed, 1070 insertions(+), 789 deletions(-) delete mode 100644 reginfo.c create mode 100644 test_sme_aarch64.s