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([2602:ae:1547:e101:250:b6ff:fe24:58ae]) by smtp.gmail.com with ESMTPSA id 184-20020a6302c1000000b003fcf1279c84sm5562151pgc.33.2022.06.04.16.10.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jun 2022 16:10:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 0/3] target/riscv: Fix issue 1060 Date: Sat, 4 Jun 2022 23:10:01 +0000 Message-Id: <20220604231004.49990-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This issue concerns the value of mtval for illegal instruction exceptions, and came with a great test case. The fix is just two lines, in the first patch, but I noticed some cleanups on the way. r~ Richard Henderson (3): target/riscv: Set env->bins in gen_exception_illegal target/riscv: Remove generate_exception_mtval target/riscv: Minimize the calls to decode_save_opc target/riscv/translate.c | 31 +++++------ .../riscv/insn_trans/trans_privileged.c.inc | 4 ++ target/riscv/insn_trans/trans_rvh.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + tests/tcg/riscv64/Makefile.softmmu-target | 21 ++++++++ tests/tcg/riscv64/issue1060.S | 53 +++++++++++++++++++ tests/tcg/riscv64/semihost.ld | 21 ++++++++ 7 files changed, 116 insertions(+), 18 deletions(-) create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target create mode 100644 tests/tcg/riscv64/issue1060.S create mode 100644 tests/tcg/riscv64/semihost.ld