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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 00/45] target/arm: Cleanups, new features, new cpus Date: Sat, 30 Apr 2022 22:49:42 -0700 Message-Id: <20220501055028.646596-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Changes for v4: * Rebase on master, where the first third is upstream. * Split changes to add_cpreg_to_hashtable into bite sized chunks. * Add ARM_CP_EL3_NO_EL2_{UNDEF,KEEP} flags. * Fix access check for SCXTNUM_ELx (damien). Patches lacking review: 05-target-arm-Reorg-ARMCPRegInfo-type-field-bits.patch 06-target-arm-Avoid-bare-abort-or-assert-0.patch 10-target-arm-Drop-always-true-test-in-define_arm_vh.patch 11-target-arm-Store-cpregs-key-in-the-hash-table-dir.patch 12-target-arm-Merge-allocation-of-the-cpreg-and-its-.patch 13-target-arm-Hoist-computation-of-key-in-add_cpreg_.patch 14-target-arm-Consolidate-cpreg-updates-in-add_cpreg.patch 15-target-arm-Use-bool-for-is64-and-ns-in-add_cpreg_.patch 16-target-arm-Hoist-isbanked-computation-in-add_cpre.patch 17-target-arm-Perform-override-check-early-in-add_cp.patch 18-target-arm-Reformat-comments-in-add_cpreg_to_hash.patch 19-target-arm-Remove-HOST_BIG_ENDIAN-ifdef-in-add_cp.patch 20-target-arm-Handle-cpreg-registration-for-missing-.patch 21-target-arm-Drop-EL3-no-EL2-fallbacks.patch 22-target-arm-Merge-zcr-reginfo.patch 34-target-arm-Add-minimal-RAS-registers.patch 41-target-arm-Enable-FEAT_CSV2_2-for-cpu-max.patch r~ Richard Henderson (45): target/arm: Split out cpregs.h target/arm: Reorg CPAccessResult and access_check_cp_reg target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h target/arm: Make some more cpreg data static const target/arm: Reorg ARMCPRegInfo type field bits target/arm: Avoid bare abort() or assert(0) target/arm: Change cpreg access permissions to enum target/arm: Name CPState type target/arm: Name CPSecureState type target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases target/arm: Store cpregs key in the hash table directly target/arm: Merge allocation of the cpreg and its name target/arm: Hoist computation of key in add_cpreg_to_hashtable target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable target/arm: Hoist isbanked computation in add_cpreg_to_hashtable target/arm: Perform override check early in add_cpreg_to_hashtable target/arm: Reformat comments in add_cpreg_to_hashtable target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable target/arm: Handle cpreg registration for missing EL target/arm: Drop EL3 no EL2 fallbacks target/arm: Merge zcr reginfo target/arm: Add isar predicates for FEAT_Debugv8p2 target/arm: Adjust definition of CONTEXTIDR_EL2 target/arm: Move cortex impdef sysregs to cpu_tcg.c target/arm: Update qemu-system-arm -cpu max to cortex-a57 target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max target/arm: Split out aa32_max_features target/arm: Annotate arm_max_initfn with FEAT identifiers target/arm: Use field names for manipulating EL2 and EL3 modes target/arm: Enable FEAT_Debugv8p2 for -cpu max target/arm: Enable FEAT_Debugv8p4 for -cpu max target/arm: Add isar_feature_{aa64,any}_ras target/arm: Add minimal RAS registers target/arm: Enable SCR and HCR bits for RAS target/arm: Implement virtual SError exceptions target/arm: Implement ESB instruction target/arm: Enable FEAT_RAS for -cpu max target/arm: Enable FEAT_IESB for -cpu max target/arm: Enable FEAT_CSV2 for -cpu max target/arm: Enable FEAT_CSV2_2 for -cpu max target/arm: Enable FEAT_CSV3 for -cpu max target/arm: Enable FEAT_DGH for -cpu max target/arm: Define cortex-a76 target/arm: Define neoverse-n1 docs/system/arm/emulation.rst | 10 + docs/system/arm/virt.rst | 2 + target/arm/cpregs.h | 462 +++++++++++++++++ target/arm/cpu.h | 416 ++-------------- target/arm/helper.h | 1 + target/arm/internals.h | 16 + target/arm/syndrome.h | 5 + target/arm/a32.decode | 16 +- target/arm/t32.decode | 18 +- hw/arm/pxa2xx.c | 2 +- hw/arm/pxa2xx_pic.c | 2 +- hw/arm/sbsa-ref.c | 2 + hw/arm/virt.c | 2 + hw/intc/arm_gicv3_cpuif.c | 6 +- hw/intc/arm_gicv3_kvm.c | 3 +- target/arm/cpu.c | 84 ++-- target/arm/cpu64.c | 353 +++++++------ target/arm/cpu_tcg.c | 232 ++++++--- target/arm/gdbstub.c | 5 +- target/arm/helper.c | 909 ++++++++++++++++++---------------- target/arm/hvf/hvf.c | 2 +- target/arm/kvm-stub.c | 4 +- target/arm/kvm.c | 4 +- target/arm/machine.c | 4 +- target/arm/op_helper.c | 100 ++-- target/arm/translate-a64.c | 32 +- target/arm/translate-neon.c | 2 +- target/arm/translate.c | 36 +- 28 files changed, 1604 insertions(+), 1126 deletions(-) create mode 100644 target/arm/cpregs.h