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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id y131-20020a626489000000b00505a8f36965sm15655813pfb.184.2022.04.26.09.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 09:30:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 00/47] target/arm: Use tcg_constant Date: Tue, 26 Apr 2022 09:29:56 -0700 Message-Id: <20220426163043.100432-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split the tcg_constant patches out of my larger v3 cleanups patch set, and then split the 5 patches into tiny bites. r~ Richard Henderson (47): target/arm: Use tcg_constant in gen_probe_access target/arm: Use tcg_constant in gen_mte_check* target/arm: Use tcg_constant in gen_exception* target/arm: Use tcg_constant in gen_adc_CC target/arm: Use tcg_constant in handle_msr_i target/arm: Use tcg_constant in handle_sys target/arm: Use tcg_constant in disas_exc target/arm: Use tcg_constant in gen_compare_and_swap_pair target/arm: Use tcg_constant in disas_ld_lit target/arm: Use tcg_constant in disas_ldst_* target/arm: Use tcg_constant in disas_add_sum_imm* target/arm: Use tcg_constant in disas_movw_imm target/arm: Use tcg_constant in shift_reg_imm target/arm: Use tcg_constant in disas_cond_select target/arm: Use tcg_constant in handle_{rev16,crc32} target/arm: Use tcg_constant in disas_data_proc_2src target/arm: Use tcg_constant in disas_fp* target/arm: Use tcg_constant in simd shift expanders target/arm: Use tcg_constant in simd fp/int conversion target/arm: Use tcg_constant in 2misc expanders target/arm: Use tcg_constant in balance of translate-a64.c target/arm: Use tcg_constant for aa32 exceptions target/arm: Use tcg_constant for disas_iwmmxt_insn target/arm: Use tcg_constant for gen_{msr,mrs} target/arm: Use tcg_constant for vector shift expanders target/arm: Use tcg_constant for do_coproc_insn target/arm: Use tcg_constant for gen_srs target/arm: Use tcg_constant for op_s_{rri,rxi}_rot target/arm: Use tcg_constant for MOVW, UMAAL, CRC32 target/arm: Use tcg_constant for v7m MRS, MSR target/arm: Use tcg_constant for TT, SAT, SMMLA target/arm: Use tcg_constant in LDM, STM target/arm: Use tcg_constant in CLRM, DLS, WLS, LE target/arm: Use tcg_constant in trans_CPS_v7m target/arm: Use tcg_constant in trans_CSEL target/arm: Use tcg_constant for trans_INDEX_* target/arm: Use tcg_constant in SINCDEC, INCDEC target/arm: Use tcg_constant in FCPY, CPY target/arm: Use tcg_constant in {incr,wrap}_last_active target/arm: Use tcg_constant in do_clast_scalar target/arm: Use tcg_constant in WHILE target/arm: Use tcg_constant in LD1, ST1 target/arm: Use tcg_constant in SUBR target/arm: Use tcg_constant in do_zzi_{sat,ool}, do_fp_imm target/arm: Use tcg_constant for predicate descriptors target/arm: Use tcg_constant for do_brk{2,3} target/arm: Use tcg_constant for vector descriptor target/arm/translate-a64.c | 302 +++++++++++-------------------------- target/arm/translate-sve.c | 202 +++++++++---------------- target/arm/translate.c | 244 ++++++++++-------------------- 3 files changed, 241 insertions(+), 507 deletions(-)