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[0/2] target/riscv: Annotate atomic operations

Message ID 20220401125948.79292-1-richard.henderson@linaro.org
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Series target/riscv: Annotate atomic operations | expand

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Richard Henderson April 1, 2022, 12:59 p.m. UTC 
If an atomic operation fails on RISC-V, we want to generate
a store/amo fault and not a load fault.

Annotate amo insns, so that we can recognize them after unwinding.
Transform the implementation access type to store/amo for reporting.


r~


Richard Henderson (2):
  target/riscv: Use cpu_loop_exit_restore directly from mmu faults
  target/riscv: Mark amo insns during translation

 target/riscv/cpu.h                      | 15 ++++++
 target/riscv/cpu.c                      |  3 ++
 target/riscv/cpu_helper.c               | 62 +++++++++++++++++--------
 target/riscv/translate.c                |  9 ++++
 target/riscv/insn_trans/trans_rva.c.inc | 11 ++++-
 5 files changed, 79 insertions(+), 21 deletions(-)

Comments

Alistair Francis April 12, 2022, 12:10 a.m. UTC | #1 
On Fri, Apr 1, 2022 at 11:00 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> If an atomic operation fails on RISC-V, we want to generate
> a store/amo fault and not a load fault.
>
> Annotate amo insns, so that we can recognize them after unwinding.
> Transform the implementation access type to store/amo for reporting.
>
>
> r~
>
>
> Richard Henderson (2):
>   target/riscv: Use cpu_loop_exit_restore directly from mmu faults
>   target/riscv: Mark amo insns during translation
>
>  target/riscv/cpu.h                      | 15 ++++++
>  target/riscv/cpu.c                      |  3 ++
>  target/riscv/cpu_helper.c               | 62 +++++++++++++++++--------
>  target/riscv/translate.c                |  9 ++++
>  target/riscv/insn_trans/trans_rva.c.inc | 11 ++++-
>  5 files changed, 79 insertions(+), 21 deletions(-)

Thanks!

Applied to riscv-to-apply.next

Alistair

>
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> 2.25.1
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