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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b14sm7837698wrd.24.2021.11.26.08.39.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Nov 2021 08:39:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2? 0/2] arm_gicv3: Fix handling of LPIs in list registers Date: Fri, 26 Nov 2021 16:39:13 +0000 Message-Id: <20211126163915.1048353-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::435 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Shashi Mallela , =?utf-8?q?Alex_Benn=C3=A9e?= , Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" (Marc: cc'd you on this one in case you're still using QEMU to test KVM stuff with, in which case you might have run into the bug this is fixing.) It is valid for an OS to put virtual interrupt ID values into the list registers ICH_LR which are greater than 1023. This corresponds to (for example) KVM running as an L1 guest inside emulated QEMU and using the in-kernel emulated ITS to give a (nested) L2 guest an ITS. LPIs are delivered by the L1 kernel to the L2 guest via the list registers in the same way as non-LPI interrupts. QEMU's code for handling writes to ICV_IARn (which happen when the L2 guest acknowledges an interrupt) and to ICV_EOIRn (which happen at the end of the interrupt) did not consider LPIs, so it would incorrectly treat interrupt IDs above 1023 as invalid, with the effect that a read to ICV_IARn would return the correct interrupt ID number but not actually mark the interrupt active or set the CPU priority accordingly, and a write to ICV_EOIRn would do nothing. This bug doesn't seem to have any visible effect on Linux L2 guests most of the time, because the two bugs cancel each other out: we neither mark the interrupt active nor deactivate it. However it does mean that the L2 vCPU priority while the LPI handler is running will not be correct, so the interrupt handler could be unexpectedly interrupted by a different interrupt. (I haven't observed this; I found the ICV_IARn bug by code inspection, and then the ICV_EOIRn bug by figuring out why fixing ICV_IARn broke L2 guests :-)) This isn't a regression -- we've behaved like this since the GICv3 support for virtualization was first implemented. I'm tempted to put it into 6.2 anyway, though. Patch 1 abstracts out the test we were using already elsewhere in the code into its own function, and patch 2 uses it to fix the EOIR and IAR behaviour. Based-on: 20211124202005.989935-1-peter.maydell@linaro.org ("[PATCH v2] hw/intc/arm_gicv3: Update cached state after LPI state changes") Peter Maydell (2): hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function hw/intc/arm_gicv3: fix handling of LPIs in list registers hw/intc/gicv3_internal.h | 13 +++++++++++++ hw/intc/arm_gicv3_cpuif.c | 9 ++++----- 2 files changed, 17 insertions(+), 5 deletions(-) Reviewed-by: Marc Zyngier