From patchwork Wed Oct 20 03:16:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515987 Delivered-To: patch@linaro.org Received: by 2002:adf:a11e:0:0:0:0:0 with SMTP id o30csp1322514wro; Tue, 19 Oct 2021 20:26:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4rPOqEDZ4g+YrWHC2chXBmD943h6XJjZCEEuTOy3dOcXrEAzvaz3Al9X61RU8nRt1TJN8 X-Received: by 2002:aca:dbc2:: with SMTP id s185mr6965390oig.141.1634700408559; Tue, 19 Oct 2021 20:26:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1634700408; cv=none; d=google.com; s=arc-20160816; b=peY2FLwNJozoy4uWrXtrrKYxWw7QsQNmIWrFB7aA7vTaEBkqOqpoV6bfvSC+dfGYlN rrcVVuC8mFolwJQ/e4ywwZEXHXgJlTktgMSc81WN7pOJb7PiBkIgQDMe2r0e7QirHgwW 4uXOvQlJUumOX5VfsSiSCP/St8d+9ZIbbD/F0Djl6NQNzx5Nm3idTqHCb91NwZdQgd1D TS6DcQcFEv22ODVg5CgchoxVfl/FDOQW/Og47H5237U7kR9g7V8CM+RYjzXyO+6iOMwY IH6OtzHPgBeCcbjx3gCyd4XSmMo0f6TV7QpVPpzzsWhtWhBmow2omRA/cSK8UzIwx5wo PA7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:to:from:dkim-signature; bh=NFxpn2R0k5C60j5k65WXwQSMBvI9nKjCadLREfX3z84=; b=WrLClvGBwCZoBau4bZ8wk2cuWjbVv84lwj0o2ZJyr/2UM7RGwo1Zi6jq1N0iDmbUQg sCTIcjxx+inbcYZyWdZm4O1y2SkmGKSoua627cljAsljRdkspO2uYkOPyQoSPLeh1CTH d+BEhp8vMrXOO0602h8H9LJ6sHmlIEC78hli+ACZZCnPV/q4zZVzjYlTRsxtjrfgLDA9 aHyDwCBkOwIXCSFvnTSqtcVQ7pOB3MMEvb0PrxG1C71aslCIUEdTV21ho0nG0Jq97CZH y/fGCSHcmVlBUQGYsjV22blsY6qKnNmxCJAouvViVvltn12DB2QjH2Y9cnj91I/Zo88Y yF0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qeaVne62; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 125si1103880oih.165.2021.10.19.20.26.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Oct 2021 20:26:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qeaVne62; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46320 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1md2Fb-00058N-RS for patch@linaro.org; Tue, 19 Oct 2021 23:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1md26P-0006fW-7H for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:17 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:43678) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1md26L-0000wm-25 for qemu-devel@nongnu.org; Tue, 19 Oct 2021 23:17:16 -0400 Received: by mail-pg1-x534.google.com with SMTP id r2so21230991pgl.10 for ; Tue, 19 Oct 2021 20:17:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=NFxpn2R0k5C60j5k65WXwQSMBvI9nKjCadLREfX3z84=; b=qeaVne62wE4WzWwlVTv8weO0PKpjJQb7jYn34OfoyGQZ5ohArNhljFa8gWa1E/El2A 8IWGqrwtCVSHrhFFdvplQJwBEslYWvZ6yaozBcJZCAvmWwfC8xKKjtI+Tf/RBTKg2TPN sSIFWFeCMqpACUZc2c8HiprM7k/iPXSWeA2mwzmEXAxemPZdj+i64D3XspmlRIGIgkG9 mJ3CJyW2/jVOG/eSbwG2WX5es3wIwx/mcyrtWKPGrJ5w5miMwYderi0raaRsLGWe3+tZ 5aPlEljWRBgT/Rs7JVNx8YxkZdd3lvzAvKepiKrlU60YCw5QauYuSaY+k5MjPkpB8oBD KXzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=NFxpn2R0k5C60j5k65WXwQSMBvI9nKjCadLREfX3z84=; b=ZOaAK+36khhpUqwc61LrUR4ox/Xkj06ba7EAuTaglgRwVfZQpmPERyMH0J35YHTvi/ VcAjjpCFYQ9j2ht0f+70Jwq8RmvqOKr7CWl+x5tHkiC66fwBum1LCxNLnYZzVKCxssPN Bc1wrCX64b2Q5KBbNmkYS7gmawPJo0Vo9PqsxyrTIcmDUFgkHPQJz7mR609KyJXxd7Vo mMryc8WFAjR24BJkgQZNoML7Ejt1FJM30WKE3Fx75Bc+Xgv8ksxgWSFJb3PvtLX2VpLl vh99tCzcY6mvDCeeA1QCBZX2T3soIi3rTRId9fvWqclBT4c7eT7ROBOfkL49+M7DPue1 tiWA== X-Gm-Message-State: AOAM531uc8QW2vARE3khIHtBvPOpCWYcKwCKGWDT++Qau2OlpJwgbOMi 5VmgrsQB7flp4rYNdsXhtCaT8qtsq+G+wg== X-Received: by 2002:a63:2a92:: with SMTP id q140mr31818693pgq.412.1634699831067; Tue, 19 Oct 2021 20:17:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id c8sm505364pjr.38.2021.10.19.20.17.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 20:17:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Date: Tue, 19 Oct 2021 20:16:54 -0700 Message-Id: <20211020031709.359469-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a partial patch set attempting to set things in the right direction for both the UXL and RV128 patch sets. r~ Changes for v6: * Rebase on riscv-to-apply.next. Changes for v5: * Fix cpu_dump, which asserted for -accel qtest. Instead of filtering CSRs explicitly in cpu_dump, let the riscv_csr_operations predicate do the job. This means we won't dump S-mode registers when RVS is not enabled, much like we currently filter on RVH. Changes for v4: * Use riscv_csrrw_debug for cpu_dump. This fixes the issue that Alistair pointed out wrt the MSTATUS.SD bit not being correct in the dump; note that gdbstub already uses riscv_csrrw_debug, and so did not have a problem. * Align the registers in cpu_dump. Changes for v3: * Fix CONFIG_ typo. * Fix ctzw typo. * Mark get_xlen unused (clang werror) * Compute MSTATUS_SD on demand. Changes for v2: * Set mxl/sxl/uxl at reset. * Set sxl/uxl in write_mstatus. Richard Henderson (15): target/riscv: Move cpu_get_tb_cpu_state out of line target/riscv: Create RISCVMXL enumeration target/riscv: Split misa.mxl and misa.ext target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl target/riscv: Add MXL/SXL/UXL to TB_FLAGS target/riscv: Use REQUIRE_64BIT in amo_check64 target/riscv: Properly check SEW in amo_op target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Use gen_arith_per_ol for RVM target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Use gen_unary_per_ol for RVB target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Use riscv_csrrw_debug for cpu_dump target/riscv: Compute mstatus.sd on demand target/riscv/cpu.h | 73 +++------ target/riscv/cpu_bits.h | 8 +- hw/riscv/boot.c | 2 +- linux-user/elfload.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- semihosting/arm-compat-semi.c | 2 +- target/riscv/cpu.c | 195 +++++++++++++----------- target/riscv/cpu_helper.c | 92 ++++++++++- target/riscv/csr.c | 104 ++++++++----- target/riscv/gdbstub.c | 10 +- target/riscv/machine.c | 10 +- target/riscv/monitor.c | 4 +- target/riscv/translate.c | 174 +++++++++++++++------ target/riscv/insn_trans/trans_rvb.c.inc | 140 +++++++++-------- target/riscv/insn_trans/trans_rvi.c.inc | 44 +++--- target/riscv/insn_trans/trans_rvm.c.inc | 36 ++++- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++-- 17 files changed, 576 insertions(+), 351 deletions(-) -- 2.25.1