[0/8] tcg: support 32-bit guest addresses as signed

Message ID	20211010174401.141339-1-richard.henderson@linaro.org
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Series	tcg: support 32-bit guest addresses as signed \| expand [0/8] tcg: support 32-bit guest addresses as signed [1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32 [2/8] accel/tcg: Split out g2h_tlbe [3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu [4/8] accel/tcg: Add guest_base_signed_addr32 for user-only [5/8] linux-user: Support TCG_TARGET_SIGNED_ADDR32 [6/8] tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32 [7/8] target/mips: Support TCG_TARGET_SIGNED_ADDR32 [8/8] target/riscv: Support TCG_TARGET_SIGNED_ADDR32

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20211010174401.141339-1-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 0/8] tcg: support 32-bit guest addresses as signed
Date: Sun, 10 Oct 2021 10:43:53 -0700
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Series

tcg: support 32-bit guest addresses as signed | expand

Message

Richard Henderson Oct. 10, 2021, 5:43 p.m. UTC

We have 2, and nearly 3, hosts that naturally produce sign-extended
values, and have to work extra hard (with 1 or 2 insns) to produce
the zero-extended address that we expect today.

However, it's a simple matter of arithmetic for the middle-end to
require sign-extended addresses instead.  For user-only, we do have
to be careful not to allow a guest object to wrap around the signed
boundary, but that's fairly easily done.

Tested with aarch64, as that's the best hw currently available.


r~


Richard Henderson (8):
  tcg: Add TCG_TARGET_SIGNED_ADDR32
  accel/tcg: Split out g2h_tlbe
  accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu
  accel/tcg: Add guest_base_signed_addr32 for user-only
  linux-user: Support TCG_TARGET_SIGNED_ADDR32
  tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32
  target/mips: Support TCG_TARGET_SIGNED_ADDR32
  target/riscv: Support TCG_TARGET_SIGNED_ADDR32

 include/exec/cpu-all.h        | 20 ++++++++---
 include/exec/cpu_ldst.h       |  3 +-
 tcg/aarch64/tcg-target-sa32.h |  7 ++++
 tcg/arm/tcg-target-sa32.h     |  1 +
 tcg/i386/tcg-target-sa32.h    |  1 +
 tcg/mips/tcg-target-sa32.h    |  9 +++++
 tcg/ppc/tcg-target-sa32.h     |  1 +
 tcg/riscv/tcg-target-sa32.h   |  5 +++
 tcg/s390x/tcg-target-sa32.h   |  1 +
 tcg/sparc/tcg-target-sa32.h   |  1 +
 tcg/tci/tcg-target-sa32.h     |  1 +
 accel/tcg/cputlb.c            | 36 +++++++++++++------
 bsd-user/main.c               |  4 +++
 linux-user/elfload.c          | 62 +++++++++++++++++++++++++-------
 linux-user/main.c             |  3 ++
 tcg/aarch64/tcg-target.c.inc  | 68 ++++++++++++++++++++++-------------
 tcg/mips/tcg-target.c.inc     | 13 ++-----
 tcg/riscv/tcg-target.c.inc    |  8 ++---
 18 files changed, 176 insertions(+), 68 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target-sa32.h
 create mode 100644 tcg/arm/tcg-target-sa32.h
 create mode 100644 tcg/i386/tcg-target-sa32.h
 create mode 100644 tcg/mips/tcg-target-sa32.h
 create mode 100644 tcg/ppc/tcg-target-sa32.h
 create mode 100644 tcg/riscv/tcg-target-sa32.h
 create mode 100644 tcg/s390x/tcg-target-sa32.h
 create mode 100644 tcg/sparc/tcg-target-sa32.h
 create mode 100644 tcg/tci/tcg-target-sa32.h

-- 
2.25.1