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envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Based-on: <20210818191920.390759-1-richard.henderson@linaro.org> ("[PATCH v3 00/66] Unaligned access for user-only") Important points: * Support unaligned accesses. * Drop requirement for 256MB alignment of code_gen_buffer. * Improvements to tcg_out_movi: - Have a tb-relative register for mips64, reducing the code size for most pointers, - Try a few 3-insn sequences, - Drop everything else into a constant pool. r~ Richard Henderson (16): tcg/mips: Support unaligned access for user-only tcg/mips: Support unaligned access for softmmu tcg/mips: Drop inline markers tcg/mips: Move TCG_AREG0 to S8 tcg/mips: Move TCG_GUEST_BASE_REG to S7 tcg/mips: Unify TCG_GUEST_BASE_REG tests tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr tcg/mips: Unset TCG_TARGET_HAS_direct_jump tcg/mips: Drop special alignment for code_gen_buffer tcg/mips: Create and use TCG_REG_TB tcg/mips: Split out tcg_out_movi_one tcg/mips: Split out tcg_out_movi_two tcg/mips: Use the constant pool for 64-bit constants tcg/mips: Aggressively use the constant pool for n64 calls tcg/mips: Try tb-relative addresses in tcg_out_movi tcg/mips: Try three insns with shift and add in tcg_out_movi tcg/mips/tcg-target.h | 17 +- tcg/region.c | 91 ----- tcg/mips/tcg-target.c.inc | 730 +++++++++++++++++++++++++++++++------- 3 files changed, 604 insertions(+), 234 deletions(-) -- 2.25.1