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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id q17sm21146132pjd.42.2021.07.20.23.41.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 23:41:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.2 00/23] tcg: gdb singlestep reorg Date: Tue, 20 Jul 2021 20:41:32 -1000 Message-Id: <20210721064155.645508-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Based-on: <20210720195439.626594-1-richard.henderson@linaro.org> ("tcg: breakpoint reorg") Consolidate all handling for gdb singlestep to 4 lines in cpu_tb_exec. Drop all of the code from target/*. Note that nios2 and sparc, lacked support for gdb singlestep entirely, which was a bit of a surprise. r~ Richard Henderson (23): accel/tcg: Handle gdb singlestep in cpu_tb_exec target/alpha: Drop checks for singlestep_enabled target/avr: Drop checks for singlestep_enabled target/cris: Drop checks for singlestep_enabled target/hexagon: Drop checks for singlestep_enabled target/arm: Drop checks for singlestep_enabled target/hppa: Drop checks for singlestep_enabled target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt target/i386: Drop check for singlestep_enabled target/m68k: Drop checks for singlestep_enabled target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP target/microblaze: Drop checks for singlestep_enabled target/mips: Fix single stepping target/mips: Drop exit checks for singlestep_enabled target/openrisc: Drop checks for singlestep_enabled target/ppc: Drop exit checks for singlestep_enabled target/riscv: Remove dead code after exception target/riscv: Remove exit_tb and lookup_and_goto_ptr target/rx: Drop checks for singlestep_enabled target/s390x: Drop check for singlestep_enabled target/sh4: Drop check for singlestep_enabled target/tricore: Drop check for singlestep_enabled target/xtensa: Drop check for singlestep_enabled target/i386/helper.h | 1 - target/rx/helper.h | 1 - target/sh4/helper.h | 1 - target/tricore/helper.h | 1 - accel/tcg/cpu-exec.c | 11 +++ target/alpha/translate.c | 13 +--- target/arm/translate-a64.c | 10 +-- target/arm/translate.c | 36 ++------- target/avr/translate.c | 19 +---- target/cris/translate.c | 16 ---- target/hexagon/translate.c | 12 +-- target/hppa/translate.c | 17 +---- target/i386/tcg/misc_helper.c | 8 -- target/i386/tcg/translate.c | 9 +-- target/m68k/translate.c | 44 +++-------- target/microblaze/translate.c | 18 +---- target/mips/tcg/translate.c | 75 +++++++++---------- target/openrisc/translate.c | 18 +---- target/ppc/translate.c | 38 ++-------- target/riscv/translate.c | 29 +------ target/rx/op_helper.c | 8 -- target/rx/translate.c | 12 +-- target/s390x/tcg/translate.c | 8 +- target/sh4/op_helper.c | 5 -- target/sh4/translate.c | 14 +--- target/tricore/op_helper.c | 7 -- target/tricore/translate.c | 14 +--- target/xtensa/translate.c | 25 ++----- .../riscv/insn_trans/trans_privileged.c.inc | 10 +-- target/riscv/insn_trans/trans_rvi.c.inc | 6 +- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 31 files changed, 118 insertions(+), 370 deletions(-) -- 2.25.1