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[142.114.142.78]) by smtp.googlemail.com with ESMTPSA id 97sm273044qte.20.2021.06.02.11.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 11:00:43 -0700 (PDT) From: Shashi Mallela To: peter.maydell@linaro.org, leif@nuviainc.com, rad@semihalf.com Subject: [PATCH v4 0/8] GICv3 LPI and ITS feature implementation Date: Wed, 2 Jun 2021 14:00:34 -0400 Message-Id: <20210602180042.111347-1-shashi.mallela@linaro.org> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::729; envelope-from=shashi.mallela@linaro.org; helo=mail-qk1-x729.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This patchset implements qemu device model for enabling physical LPI support and ITS functionality in GIC as per GICv3 specification. Both flat table and 2 level tables are implemented.The ITS commands for adding/deleting ITS table entries,trigerring LPI interrupts are implemented.Translated LPI interrupt ids are processed by redistributor to determine priority and set pending state appropriately before forwarding the same to cpu interface. The ITS feature support has been added to sbsa-ref platform as well as virt platform,wherein the emulated functionality co-exists with kvm kernel functionality. Changes in v4: - review comments addressed - redesigned the lpi pending priority determination logic to scan LPI pending table and config table right after lpi pending statechanges(SET/RESET) through gicv3_redist_update_lpi() call to determinethe highest priority lpi among the active lpis and save the details.The high priority interrupt determination logic in redistributor now usesthe saved high priority lpi details (alongside other interrupt types) instead of calling gicv3_redist_update_lpi() everytime(as in v3).This significantly reduces the call overhead associated with address_space_read of lpi config and pending tables. Testing with this new design showed no boot delays. - profiled execution of gicv3_redist_update_lpi() using perf and framegraph to confirm execution is within normal limits. Also,specifically measured execution time to be an average of 175us with linux distro testing. - All kvm_unit_tests PASS Shashi Mallela (8): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing hw/arm/sbsa-ref: add ITS support in SBSA GIC hw/arm/virt: add ITS support in virt GIC hw/arm/sbsa-ref.c | 26 +- hw/arm/virt.c | 27 +- hw/intc/arm_gicv3.c | 9 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 7 +- hw/intc/arm_gicv3_its.c | 1217 ++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 8 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 159 +++- hw/intc/gicv3_internal.h | 186 +++- hw/intc/meson.build | 1 + include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 16 + include/hw/intc/arm_gicv3_its_common.h | 39 +- target/arm/kvm_arm.h | 4 +- 16 files changed, 1694 insertions(+), 29 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c -- 2.27.0