From patchwork Fri Apr 16 21:01:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422590 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp717360jaf; Fri, 16 Apr 2021 14:03:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzDWTOnzDIpxf5D6NDMKv8sOl2GP9Q4b7KEpUz9w03ziYKjNPg17fMCyg1wRviUUsIgAP+ X-Received: by 2002:a9d:5541:: with SMTP id h1mr5030600oti.246.1618606995621; Fri, 16 Apr 2021 14:03:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618606995; cv=none; d=google.com; s=arc-20160816; b=00rRfJ5vmm7ASIhRCdJ+LaJA41YX/yLILOqEjlClJc3N2WEwaaOdePPtGDEqMgIO8T tK1YG3ImI7wF+1ac44OWF1MZZFxn1u//GOD7RKbBZuGovydOqez8CruYtoCcVkHepNKF 1fcMQPqGlXQj7TuG0zo4Qf/XFGh16umL5IPO7rRgKPKJ+7Ko23jOpDLEHlmDjVHDj7jb s7dud4poteC1XeUg1iPeWdUTZoscWMxjjlKmTlnRtqYSIYypyjj1wCgbvq8a5v08p7Za 9BbuOwYQyC+oICPLFtbXAEFLweLMJxZwHYjfvyAmKecewwUPzJIJC+epsCFwCzXe3yg8 xGvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:to:from:dkim-signature; bh=ie9r6EOQypZoQYkbRn9pO7nDggqaoqaomu+rCPA0MmU=; b=xqxnYEc95aGQtV7WVaddBKMB2yQVY1p8xuR/IRVCbC/ylVZpZUOWRkVw3JAxGlSoVd wq3BwKz3CmgfARBLOs7WEEUWH/RrglH5uijepmRhzOj9xDX+BlDATZ2V4KZo8WxK9s0L CX2Cnvb7q99BWA8oiIhofPAgwnG+E2LonR8+5Jp7QU5xdJGT97zg/NR0hTlHCKsGdyE7 aOiwpR4qoGiCiPscuSSKnHWt9ufzXbTOUqSQ9zqh4utvIr0A8d76lV1qtQNryn/6igQh tcFr90lchuJ/3ytthvgjciLCpUoDZE/kqBo0UOWpCNg/cee6fxH6nYzFO1StjKujhLpL +X0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=epeFFpzi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o7si6176717otp.236.2021.04.16.14.03.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 14:03:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=epeFFpzi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXVcQ-0003so-Sw for patch@linaro.org; Fri, 16 Apr 2021 17:03:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXVc0-0003pn-7p for qemu-devel@nongnu.org; Fri, 16 Apr 2021 17:02:48 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:34737) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXVbx-0000wv-25 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 17:02:48 -0400 Received: by mail-pl1-x632.google.com with SMTP id t22so14309057ply.1 for ; Fri, 16 Apr 2021 14:02:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ie9r6EOQypZoQYkbRn9pO7nDggqaoqaomu+rCPA0MmU=; b=epeFFpziAOMORL8aFyTO4bT0W1OpGNtSNSYlhywiiVph4Rk8+tEPVWltWraNpv96A9 +AP0AldYN4c+gIWOnJ5h2Q+7kOkwg2B2Xd3MgnNeStSdpVsSjO4J3yp30RORPuI68O/c 9c4UkxYJJjFu8bLXqQH7xDCp7BTl7SMyxQ+vZdhM5unEx+OU9MgX3u7i3EUO5EHfFYti Up3u7YtDFptg/7QGJjzmji43yb3/H7BW3SXBn396kz5qei7G8R2laPQtVs2R/FpB9H6/ G8hh8U2RPvMCEEHUiO2JB9UKdkKJUTkuiqhW5y4gbL96ep6sLaKyb1pEBVTut7gItG3e /Hng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ie9r6EOQypZoQYkbRn9pO7nDggqaoqaomu+rCPA0MmU=; b=UYT08KGlQkqAljUHZQU2p+IU9O30Z0XxfnQDdvpnmVY5Y0jbh2UCNjyuK79bdvObaP DrUEM+73+Yd0AstXZFe/VPvXtM3ZMgO0HV7RlNPIdMXODkJbnYwaDpW7pR3GunbYvnWw r3Lyi1Y2gYIcfIsRJYZ6ng5/tt1s865jmroA4RCVwyxL6jna6bBBL5rGEizbos2A4UG9 eXvOBSbDJEGe3jL5dFOznxOn1UJ+olsCJ79mzsw4YmkWXPhNtYqromhmi1bNZprKwGE4 axI8/eYQQIXVhv9xIJItkoqzlDyK4XNsNnOWi9qndkOv5mNBYT6K40dV7DVB13KlqOMh +NVw== X-Gm-Message-State: AOAM53103Pu0juSngzaETFpPDAzIZnoxAPbxV4QENJ/Za/AKPcyQgD1Y u93NhJTsXn8GFQ3EKon6VY0EA5e7BpVvyQ== X-Received: by 2002:a17:902:e843:b029:eb:8aff:360 with SMTP id t3-20020a170902e843b02900eb8aff0360mr8028411plg.1.1618606963205; Fri, 16 Apr 2021 14:02:43 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id m15sm5920640pjz.36.2021.04.16.14.02.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 14:02:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 for-6.1 00/81] target/arm: Implement SVE2 Date: Fri, 16 Apr 2021 14:01:19 -0700 Message-Id: <20210416210240.1591291-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Based-on: 20210416185959.1520974-1-richard.henderson@linaro.org ("[PATCH v4 for-6.1 00/39] target/arm: enforce alignment") And of course, since I messed up the alignment subject, our tooling isn't going to thread this properly. So: https://gitlab.com/rth7680/qemu/-/tree/tgt-arm-sve2 https://gitlab.com/rth7680/qemu/-/commit/cccb2c67e975322f006e81adb3cf5e235254f254 Changes since v4: * Rebased on mte + alignment changes. * Implement integer matrix multiply accumulate. * Change to decode to facilitate bfloat16. r~ Richard Henderson (63): target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 target/arm: Implement SVE2 Integer Multiply - Unpredicated target/arm: Implement SVE2 integer pairwise add and accumulate long target/arm: Implement SVE2 integer unary operations (predicated) target/arm: Split out saturating/rounding shifts from neon target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) target/arm: Implement SVE2 integer halving add/subtract (predicated) target/arm: Implement SVE2 integer pairwise arithmetic target/arm: Implement SVE2 saturating add/subtract (predicated) target/arm: Implement SVE2 integer add/subtract long target/arm: Implement SVE2 integer add/subtract interleaved long target/arm: Implement SVE2 integer add/subtract wide target/arm: Implement SVE2 integer multiply long target/arm: Implement PMULLB and PMULLT target/arm: Implement SVE2 bitwise shift left long target/arm: Implement SVE2 bitwise exclusive-or interleaved target/arm: Implement SVE2 bitwise permute target/arm: Implement SVE2 complex integer add target/arm: Implement SVE2 integer absolute difference and accumulate long target/arm: Implement SVE2 integer add/subtract long with carry target/arm: Implement SVE2 bitwise shift right and accumulate target/arm: Implement SVE2 bitwise shift and insert target/arm: Implement SVE2 integer absolute difference and accumulate target/arm: Implement SVE2 saturating extract narrow target/arm: Implement SVE2 SHRN, RSHRN target/arm: Implement SVE2 SQSHRUN, SQRSHRUN target/arm: Implement SVE2 UQSHRN, UQRSHRN target/arm: Implement SVE2 SQSHRN, SQRSHRN target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS target/arm: Implement SVE2 WHILERW, WHILEWR target/arm: Implement SVE2 bitwise ternary operations target/arm: Implement SVE2 saturating multiply-add long target/arm: Implement SVE2 saturating multiply-add high target/arm: Implement SVE2 integer multiply-add long target/arm: Implement SVE2 complex integer multiply-add target/arm: Implement SVE2 XAR target/arm: Pass separate addend to {U,S}DOT helpers target/arm: Pass separate addend to FCMLA helpers target/arm: Split out formats for 2 vectors + 1 index target/arm: Split out formats for 3 vectors + 1 index target/arm: Implement SVE2 integer multiply (indexed) target/arm: Implement SVE2 integer multiply-add (indexed) target/arm: Implement SVE2 saturating multiply-add high (indexed) target/arm: Implement SVE2 saturating multiply-add (indexed) target/arm: Implement SVE2 saturating multiply (indexed) target/arm: Implement SVE2 signed saturating doubling multiply high target/arm: Implement SVE2 saturating multiply high (indexed) target/arm: Implement SVE mixed sign dot product (indexed) target/arm: Implement SVE mixed sign dot product target/arm: Implement SVE2 crypto unary operations target/arm: Implement SVE2 crypto destructive binary operations target/arm: Implement SVE2 crypto constructive binary operations target/arm: Share table of sve load functions target/arm: Implement SVE2 LD1RO target/arm: Implement 128-bit ZIP, UZP, TRN target/arm: Implement aarch64 SUDOT, USDOT target/arm: Split out do_neon_ddda_fpst target/arm: Remove unused fpst from VDOT_scalar target/arm: Fix decode for VDOT (indexed) target/arm: Split decode of VSDOT and VUDOT target/arm: Implement aarch32 VSUDOT, VUSDOT target/arm: Implement integer matrix multiply accumulate target/arm: Enable SVE2 and some extensions Stephen Long (18): target/arm: Implement SVE2 floating-point pairwise target/arm: Implement SVE2 MATCH, NMATCH target/arm: Implement SVE2 ADDHNB, ADDHNT target/arm: Implement SVE2 RADDHNB, RADDHNT target/arm: Implement SVE2 SUBHNB, SUBHNT target/arm: Implement SVE2 RSUBHNB, RSUBHNT target/arm: Implement SVE2 HISTCNT, HISTSEG target/arm: Implement SVE2 scatter store insns target/arm: Implement SVE2 gather load insns target/arm: Implement SVE2 FMMLA target/arm: Implement SVE2 SPLICE, EXT target/arm: Implement SVE2 TBL, TBX target/arm: Implement SVE2 FCVTNT target/arm: Implement SVE2 FCVTLT target/arm: Implement SVE2 FCVTXNT, FCVTX target/arm: Implement SVE2 FLOGB target/arm: Implement SVE2 bitwise shift immediate target/arm: Implement SVE2 fp multiply-add long target/arm/cpu.h | 66 + target/arm/helper-sve.h | 681 ++++++- target/arm/helper.h | 111 +- target/arm/translate-a64.h | 3 + target/arm/vec_internal.h | 143 ++ target/arm/neon-shared.decode | 24 +- target/arm/sve.decode | 525 +++++- target/arm/cpu.c | 1 + target/arm/cpu64.c | 13 + target/arm/helper.c | 3 +- target/arm/kvm64.c | 11 + target/arm/neon_helper.c | 507 +---- target/arm/sve_helper.c | 1904 ++++++++++++++++++- target/arm/translate-a64.c | 111 +- target/arm/translate-sve.c | 3117 +++++++++++++++++++++++++++++-- target/arm/vec_helper.c | 854 ++++++++- target/arm/translate-neon.c.inc | 231 ++- 17 files changed, 7367 insertions(+), 938 deletions(-) -- 2.25.1