mbox series

[v5,for-6.1,00/81] target/arm: Implement SVE2

Message ID 20210416210240.1591291-1-richard.henderson@linaro.org
Headers show
Series target/arm: Implement SVE2 | expand

Message

Richard Henderson April 16, 2021, 9:01 p.m. UTC 
Based-on: 20210416185959.1520974-1-richard.henderson@linaro.org
("[PATCH v4 for-6.1 00/39] target/arm: enforce alignment")

And of course, since I messed up the alignment subject, our tooling
isn't going to thread this properly.  So:

https://gitlab.com/rth7680/qemu/-/tree/tgt-arm-sve2
https://gitlab.com/rth7680/qemu/-/commit/cccb2c67e975322f006e81adb3cf5e235254f254

Changes since v4:
  * Rebased on mte + alignment changes.
  * Implement integer matrix multiply accumulate.
  * Change to decode to facilitate bfloat16.


r~


Richard Henderson (63):
  target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
  target/arm: Implement SVE2 Integer Multiply - Unpredicated
  target/arm: Implement SVE2 integer pairwise add and accumulate long
  target/arm: Implement SVE2 integer unary operations (predicated)
  target/arm: Split out saturating/rounding shifts from neon
  target/arm: Implement SVE2 saturating/rounding bitwise shift left
    (predicated)
  target/arm: Implement SVE2 integer halving add/subtract (predicated)
  target/arm: Implement SVE2 integer pairwise arithmetic
  target/arm: Implement SVE2 saturating add/subtract (predicated)
  target/arm: Implement SVE2 integer add/subtract long
  target/arm: Implement SVE2 integer add/subtract interleaved long
  target/arm: Implement SVE2 integer add/subtract wide
  target/arm: Implement SVE2 integer multiply long
  target/arm: Implement PMULLB and PMULLT
  target/arm: Implement SVE2 bitwise shift left long
  target/arm: Implement SVE2 bitwise exclusive-or interleaved
  target/arm: Implement SVE2 bitwise permute
  target/arm: Implement SVE2 complex integer add
  target/arm: Implement SVE2 integer absolute difference and accumulate
    long
  target/arm: Implement SVE2 integer add/subtract long with carry
  target/arm: Implement SVE2 bitwise shift right and accumulate
  target/arm: Implement SVE2 bitwise shift and insert
  target/arm: Implement SVE2 integer absolute difference and accumulate
  target/arm: Implement SVE2 saturating extract narrow
  target/arm: Implement SVE2 SHRN, RSHRN
  target/arm: Implement SVE2 SQSHRUN, SQRSHRUN
  target/arm: Implement SVE2 UQSHRN, UQRSHRN
  target/arm: Implement SVE2 SQSHRN, SQRSHRN
  target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
  target/arm: Implement SVE2 WHILERW, WHILEWR
  target/arm: Implement SVE2 bitwise ternary operations
  target/arm: Implement SVE2 saturating multiply-add long
  target/arm: Implement SVE2 saturating multiply-add high
  target/arm: Implement SVE2 integer multiply-add long
  target/arm: Implement SVE2 complex integer multiply-add
  target/arm: Implement SVE2 XAR
  target/arm: Pass separate addend to {U,S}DOT helpers
  target/arm: Pass separate addend to FCMLA helpers
  target/arm: Split out formats for 2 vectors + 1 index
  target/arm: Split out formats for 3 vectors + 1 index
  target/arm: Implement SVE2 integer multiply (indexed)
  target/arm: Implement SVE2 integer multiply-add (indexed)
  target/arm: Implement SVE2 saturating multiply-add high (indexed)
  target/arm: Implement SVE2 saturating multiply-add (indexed)
  target/arm: Implement SVE2 saturating multiply (indexed)
  target/arm: Implement SVE2 signed saturating doubling multiply high
  target/arm: Implement SVE2 saturating multiply high (indexed)
  target/arm: Implement SVE mixed sign dot product (indexed)
  target/arm: Implement SVE mixed sign dot product
  target/arm: Implement SVE2 crypto unary operations
  target/arm: Implement SVE2 crypto destructive binary operations
  target/arm: Implement SVE2 crypto constructive binary operations
  target/arm: Share table of sve load functions
  target/arm: Implement SVE2 LD1RO
  target/arm: Implement 128-bit ZIP, UZP, TRN
  target/arm: Implement aarch64 SUDOT, USDOT
  target/arm: Split out do_neon_ddda_fpst
  target/arm: Remove unused fpst from VDOT_scalar
  target/arm: Fix decode for VDOT (indexed)
  target/arm: Split decode of VSDOT and VUDOT
  target/arm: Implement aarch32 VSUDOT, VUSDOT
  target/arm: Implement integer matrix multiply accumulate
  target/arm: Enable SVE2 and some extensions

Stephen Long (18):
  target/arm: Implement SVE2 floating-point pairwise
  target/arm: Implement SVE2 MATCH, NMATCH
  target/arm: Implement SVE2 ADDHNB, ADDHNT
  target/arm: Implement SVE2 RADDHNB, RADDHNT
  target/arm: Implement SVE2 SUBHNB, SUBHNT
  target/arm: Implement SVE2 RSUBHNB, RSUBHNT
  target/arm: Implement SVE2 HISTCNT, HISTSEG
  target/arm: Implement SVE2 scatter store insns
  target/arm: Implement SVE2 gather load insns
  target/arm: Implement SVE2 FMMLA
  target/arm: Implement SVE2 SPLICE, EXT
  target/arm: Implement SVE2 TBL, TBX
  target/arm: Implement SVE2 FCVTNT
  target/arm: Implement SVE2 FCVTLT
  target/arm: Implement SVE2 FCVTXNT, FCVTX
  target/arm: Implement SVE2 FLOGB
  target/arm: Implement SVE2 bitwise shift immediate
  target/arm: Implement SVE2 fp multiply-add long

 target/arm/cpu.h                |   66 +
 target/arm/helper-sve.h         |  681 ++++++-
 target/arm/helper.h             |  111 +-
 target/arm/translate-a64.h      |    3 +
 target/arm/vec_internal.h       |  143 ++
 target/arm/neon-shared.decode   |   24 +-
 target/arm/sve.decode           |  525 +++++-
 target/arm/cpu.c                |    1 +
 target/arm/cpu64.c              |   13 +
 target/arm/helper.c             |    3 +-
 target/arm/kvm64.c              |   11 +
 target/arm/neon_helper.c        |  507 +----
 target/arm/sve_helper.c         | 1904 ++++++++++++++++++-
 target/arm/translate-a64.c      |  111 +-
 target/arm/translate-sve.c      | 3117 +++++++++++++++++++++++++++++--
 target/arm/vec_helper.c         |  854 ++++++++-
 target/arm/translate-neon.c.inc |  231 ++-
 17 files changed, 7367 insertions(+), 938 deletions(-)

-- 
2.25.1

Comments

no-reply@patchew.org April 16, 2021, 10:46 p.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/20210416210240.1591291-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210416210240.1591291-1-richard.henderson@linaro.org
Subject: [PATCH v5 for-6.1 00/81] target/arm: Implement SVE2

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20210416210240.1591291-1-richard.henderson@linaro.org -> patchew/20210416210240.1591291-1-richard.henderson@linaro.org
Switched to a new branch 'test'
9b57850 target/arm: Enable SVE2 and some extensions
ef27737 target/arm: Implement integer matrix multiply accumulate
37e3a60 target/arm: Implement aarch32 VSUDOT, VUSDOT
2418ef0 target/arm: Split decode of VSDOT and VUDOT
36777eb target/arm: Fix decode for VDOT (indexed)
85ce0a8 target/arm: Remove unused fpst from VDOT_scalar
5a12019 target/arm: Split out do_neon_ddda_fpst
52cd36c target/arm: Implement aarch64 SUDOT, USDOT
6212a60 target/arm: Implement SVE2 fp multiply-add long
fc626ae target/arm: Implement SVE2 bitwise shift immediate
ea844f4 target/arm: Implement 128-bit ZIP, UZP, TRN
cb4aff9 target/arm: Implement SVE2 LD1RO
406b15e target/arm: Share table of sve load functions
2aaa71d target/arm: Implement SVE2 FLOGB
43874d7 target/arm: Implement SVE2 FCVTXNT, FCVTX
3b7c16b target/arm: Implement SVE2 FCVTLT
db7cc0d target/arm: Implement SVE2 FCVTNT
f178783 target/arm: Implement SVE2 TBL, TBX
7855ae6 target/arm: Implement SVE2 crypto constructive binary operations
95dbbf6 target/arm: Implement SVE2 crypto destructive binary operations
8271888 target/arm: Implement SVE2 crypto unary operations
5a952bf target/arm: Implement SVE mixed sign dot product
f6bb4a2 target/arm: Implement SVE mixed sign dot product (indexed)
baedaa8 target/arm: Implement SVE2 saturating multiply high (indexed)
bf9a562 target/arm: Implement SVE2 signed saturating doubling multiply high
41d13d4 target/arm: Implement SVE2 saturating multiply (indexed)
7599063 target/arm: Implement SVE2 saturating multiply-add (indexed)
f6e99e5 target/arm: Implement SVE2 saturating multiply-add high (indexed)
976c0b7 target/arm: Implement SVE2 integer multiply-add (indexed)
d10bf6c target/arm: Implement SVE2 integer multiply (indexed)
606d6a4 target/arm: Split out formats for 3 vectors + 1 index
d29fbe1 target/arm: Split out formats for 2 vectors + 1 index
25606ae target/arm: Pass separate addend to FCMLA helpers
94b092e target/arm: Pass separate addend to {U, S}DOT helpers
1246231 target/arm: Implement SVE2 SPLICE, EXT
a23046a target/arm: Implement SVE2 FMMLA
861aad4 target/arm: Implement SVE2 gather load insns
2a53508 target/arm: Implement SVE2 scatter store insns
eb709e4 target/arm: Implement SVE2 XAR
44a5278 target/arm: Implement SVE2 HISTCNT, HISTSEG
7d2eb26 target/arm: Implement SVE2 RSUBHNB, RSUBHNT
2ea5ccf target/arm: Implement SVE2 SUBHNB, SUBHNT
14e62a9 target/arm: Implement SVE2 RADDHNB, RADDHNT
3573c67 target/arm: Implement SVE2 ADDHNB, ADDHNT
23fa167 target/arm: Implement SVE2 complex integer multiply-add
72c82f6 target/arm: Implement SVE2 integer multiply-add long
4213a0c target/arm: Implement SVE2 saturating multiply-add high
a80cca3 target/arm: Implement SVE2 saturating multiply-add long
17d9528 target/arm: Implement SVE2 MATCH, NMATCH
908209b target/arm: Implement SVE2 bitwise ternary operations
37197bf target/arm: Implement SVE2 WHILERW, WHILEWR
fb03afc target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
e445d2f target/arm: Implement SVE2 SQSHRN, SQRSHRN
a77122a target/arm: Implement SVE2 UQSHRN, UQRSHRN
b4f0efd target/arm: Implement SVE2 SQSHRUN, SQRSHRUN
9f3f360 target/arm: Implement SVE2 SHRN, RSHRN
a3021fd target/arm: Implement SVE2 floating-point pairwise
f34ad54 target/arm: Implement SVE2 saturating extract narrow
551d3aa target/arm: Implement SVE2 integer absolute difference and accumulate
63c7d93 target/arm: Implement SVE2 bitwise shift and insert
4a1d236 target/arm: Implement SVE2 bitwise shift right and accumulate
376b2fa target/arm: Implement SVE2 integer add/subtract long with carry
4ead521 target/arm: Implement SVE2 integer absolute difference and accumulate long
90015d6 target/arm: Implement SVE2 complex integer add
d706d5b target/arm: Implement SVE2 bitwise permute
f0dd83e target/arm: Implement SVE2 bitwise exclusive-or interleaved
327320f target/arm: Implement SVE2 bitwise shift left long
d3ef34e target/arm: Implement PMULLB and PMULLT
2445ba3 target/arm: Implement SVE2 integer multiply long
6eda9e2 target/arm: Implement SVE2 integer add/subtract wide
a9bacf4 target/arm: Implement SVE2 integer add/subtract interleaved long
e57041a target/arm: Implement SVE2 integer add/subtract long
04a3012 target/arm: Implement SVE2 saturating add/subtract (predicated)
e3383b5 target/arm: Implement SVE2 integer pairwise arithmetic
26d40f6 target/arm: Implement SVE2 integer halving add/subtract (predicated)
07189f2 target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated)
d49b1f8 target/arm: Split out saturating/rounding shifts from neon
527bf6e target/arm: Implement SVE2 integer unary operations (predicated)
7aa272a target/arm: Implement SVE2 integer pairwise add and accumulate long
6021e08 target/arm: Implement SVE2 Integer Multiply - Unpredicated
8e35dfe target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2

=== OUTPUT BEGIN ===
1/81 Checking commit 8e35dfe72cf6 (target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2)
2/81 Checking commit 6021e08a94d8 (target/arm: Implement SVE2 Integer Multiply - Unpredicated)
3/81 Checking commit 7aa272a846c5 (target/arm: Implement SVE2 integer pairwise add and accumulate long)
4/81 Checking commit 527bf6e4d279 (target/arm: Implement SVE2 integer unary operations (predicated))
5/81 Checking commit d49b1f870cae (target/arm: Split out saturating/rounding shifts from neon)
6/81 Checking commit 07189f24ca72 (target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated))
7/81 Checking commit 26d40f670050 (target/arm: Implement SVE2 integer halving add/subtract (predicated))
8/81 Checking commit e3383b504be3 (target/arm: Implement SVE2 integer pairwise arithmetic)
9/81 Checking commit 04a301299b1a (target/arm: Implement SVE2 saturating add/subtract (predicated))
10/81 Checking commit e57041af84a9 (target/arm: Implement SVE2 integer add/subtract long)
11/81 Checking commit a9bacf45ba80 (target/arm: Implement SVE2 integer add/subtract interleaved long)
12/81 Checking commit 6eda9e289f37 (target/arm: Implement SVE2 integer add/subtract wide)
13/81 Checking commit 2445ba3787da (target/arm: Implement SVE2 integer multiply long)
14/81 Checking commit d3ef34ec2141 (target/arm: Implement PMULLB and PMULLT)
15/81 Checking commit 327320f378d5 (target/arm: Implement SVE2 bitwise shift left long)
16/81 Checking commit f0dd83e4594f (target/arm: Implement SVE2 bitwise exclusive-or interleaved)
17/81 Checking commit d706d5ba4add (target/arm: Implement SVE2 bitwise permute)
18/81 Checking commit 90015d616658 (target/arm: Implement SVE2 complex integer add)
19/81 Checking commit 4ead52128c3c (target/arm: Implement SVE2 integer absolute difference and accumulate long)
20/81 Checking commit 376b2fa2e36c (target/arm: Implement SVE2 integer add/subtract long with carry)
21/81 Checking commit 4a1d236e6934 (target/arm: Implement SVE2 bitwise shift right and accumulate)
22/81 Checking commit 63c7d93706a0 (target/arm: Implement SVE2 bitwise shift and insert)
23/81 Checking commit 551d3aadfb08 (target/arm: Implement SVE2 integer absolute difference and accumulate)
24/81 Checking commit f34ad54db9c4 (target/arm: Implement SVE2 saturating extract narrow)
25/81 Checking commit a3021fdb45cf (target/arm: Implement SVE2 floating-point pairwise)
26/81 Checking commit 9f3f360a001b (target/arm: Implement SVE2 SHRN, RSHRN)
27/81 Checking commit b4f0efd4e65a (target/arm: Implement SVE2 SQSHRUN, SQRSHRUN)
28/81 Checking commit a77122a53b89 (target/arm: Implement SVE2 UQSHRN, UQRSHRN)
29/81 Checking commit e445d2fb3a14 (target/arm: Implement SVE2 SQSHRN, SQRSHRN)
30/81 Checking commit fb03afc6ad92 (target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS)
31/81 Checking commit 37197bf54811 (target/arm: Implement SVE2 WHILERW, WHILEWR)
32/81 Checking commit 908209ba43bf (target/arm: Implement SVE2 bitwise ternary operations)
33/81 Checking commit 17d952809154 (target/arm: Implement SVE2 MATCH, NMATCH)
34/81 Checking commit a80cca3ccd71 (target/arm: Implement SVE2 saturating multiply-add long)
35/81 Checking commit 4213a0c8c8c6 (target/arm: Implement SVE2 saturating multiply-add high)
36/81 Checking commit 72c82f64c7c5 (target/arm: Implement SVE2 integer multiply-add long)
37/81 Checking commit 23fa1670f10a (target/arm: Implement SVE2 complex integer multiply-add)
38/81 Checking commit 3573c67428e8 (target/arm: Implement SVE2 ADDHNB, ADDHNT)
39/81 Checking commit 14e62a98e9c5 (target/arm: Implement SVE2 RADDHNB, RADDHNT)
40/81 Checking commit 2ea5ccf2c452 (target/arm: Implement SVE2 SUBHNB, SUBHNT)
41/81 Checking commit 7d2eb2671339 (target/arm: Implement SVE2 RSUBHNB, RSUBHNT)
42/81 Checking commit 44a52782bd09 (target/arm: Implement SVE2 HISTCNT, HISTSEG)
43/81 Checking commit eb709e4d2346 (target/arm: Implement SVE2 XAR)
44/81 Checking commit 2a53508e4f60 (target/arm: Implement SVE2 scatter store insns)
45/81 Checking commit 861aad4ea077 (target/arm: Implement SVE2 gather load insns)
46/81 Checking commit a23046a69b9a (target/arm: Implement SVE2 FMMLA)
WARNING: line over 80 characters
#181: FILE: target/arm/translate-sve.c:7699:
+        TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);

total: 0 errors, 1 warnings, 149 lines checked

Patch 46/81 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
47/81 Checking commit 12462314cdbd (target/arm: Implement SVE2 SPLICE, EXT)
48/81 Checking commit 94b092e5304d (target/arm: Pass separate addend to {U, S}DOT helpers)
49/81 Checking commit 25606ae3bf51 (target/arm: Pass separate addend to FCMLA helpers)
50/81 Checking commit d29fbe1a8376 (target/arm: Split out formats for 2 vectors + 1 index)
51/81 Checking commit 606d6a4e1598 (target/arm: Split out formats for 3 vectors + 1 index)
52/81 Checking commit d10bf6ca96d8 (target/arm: Implement SVE2 integer multiply (indexed))
53/81 Checking commit 976c0b70930d (target/arm: Implement SVE2 integer multiply-add (indexed))
54/81 Checking commit f6e99e5de510 (target/arm: Implement SVE2 saturating multiply-add high (indexed))
55/81 Checking commit 75990637859e (target/arm: Implement SVE2 saturating multiply-add (indexed))
56/81 Checking commit 41d13d42c3a9 (target/arm: Implement SVE2 saturating multiply (indexed))
57/81 Checking commit bf9a562f0f9e (target/arm: Implement SVE2 signed saturating doubling multiply high)
58/81 Checking commit baedaa860b65 (target/arm: Implement SVE2 saturating multiply high (indexed))
59/81 Checking commit f6bb4a24301b (target/arm: Implement SVE mixed sign dot product (indexed))
60/81 Checking commit 5a952bf84da5 (target/arm: Implement SVE mixed sign dot product)
61/81 Checking commit 8271888ada1c (target/arm: Implement SVE2 crypto unary operations)
62/81 Checking commit 95dbbf6b870b (target/arm: Implement SVE2 crypto destructive binary operations)
63/81 Checking commit 7855ae6b6c4f (target/arm: Implement SVE2 crypto constructive binary operations)
64/81 Checking commit f178783e2105 (target/arm: Implement SVE2 TBL, TBX)
ERROR: space prohibited before that close parenthesis ')'
#155: FILE: target/arm/sve_helper.c:2989:
+DO_TB(d, uint64_t,   )

total: 1 errors, 0 warnings, 165 lines checked

Patch 64/81 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

65/81 Checking commit db7cc0da4bbe (target/arm: Implement SVE2 FCVTNT)
66/81 Checking commit 3b7c16bb914f (target/arm: Implement SVE2 FCVTLT)
67/81 Checking commit 43874d758de3 (target/arm: Implement SVE2 FCVTXNT, FCVTX)
68/81 Checking commit 2aaa71ddf7c3 (target/arm: Implement SVE2 FLOGB)
69/81 Checking commit 406b15e37281 (target/arm: Share table of sve load functions)
70/81 Checking commit cb4aff972d48 (target/arm: Implement SVE2 LD1RO)
71/81 Checking commit ea844f47214a (target/arm: Implement 128-bit ZIP, UZP, TRN)
ERROR: space prohibited before that close parenthesis ')'
#77: FILE: target/arm/sve_helper.c:3350:
+DO_ZIP(sve2_zip_q, Int128, )

ERROR: space prohibited before that close parenthesis ')'
#114: FILE: target/arm/sve_helper.c:3379:
+DO_UZP(sve2_uzp_q, Int128, )

ERROR: space prohibited before that close parenthesis ')'
#131: FILE: target/arm/sve_helper.c:3402:
+DO_TRN(sve2_trn_q, Int128, )

total: 3 errors, 0 warnings, 178 lines checked

Patch 71/81 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

72/81 Checking commit fc626aedd9b3 (target/arm: Implement SVE2 bitwise shift immediate)
73/81 Checking commit 6212a601b425 (target/arm: Implement SVE2 fp multiply-add long)
74/81 Checking commit 52cd36c94da8 (target/arm: Implement aarch64 SUDOT, USDOT)
75/81 Checking commit 5a1201968813 (target/arm: Split out do_neon_ddda_fpst)
76/81 Checking commit 85ce0a820f57 (target/arm: Remove unused fpst from VDOT_scalar)
77/81 Checking commit 36777eb6be81 (target/arm: Fix decode for VDOT (indexed))
78/81 Checking commit 2418ef005f51 (target/arm: Split decode of VSDOT and VUDOT)
79/81 Checking commit 37e3a60b915b (target/arm: Implement aarch32 VSUDOT, VUSDOT)
80/81 Checking commit ef2773737ef7 (target/arm: Implement integer matrix multiply accumulate)
81/81 Checking commit 9b57850fe703 (target/arm: Enable SVE2 and some extensions)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210416210240.1591291-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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