mbox series

[v2,00/24] target/arm: enforce alignment

Message ID 20201208180118.157911-1-richard.henderson@linaro.org
Headers show
Series target/arm: enforce alignment | expand

Message

Richard Henderson Dec. 8, 2020, 6 p.m. UTC 
As reported in https://bugs.launchpad.net/bugs/1905356

For version 2, I've rearranged things a bit, which has made it easy
to support SCTLR.A/CCR.UNALIGN_TRAP.  At least for non-sve code,
where we issue tcg load/store operations.  Predicated sve load/stores
will require more work within the helpers.

I've not explicitly tested the SCTLR.A support, since I don't have
any code that tries to enable it.  Though it seems obvious enough.
I will look into writing a small semihosting test case using our
existing test infrastructure shortly.


r~


Supercedes: <20201125040642.2339476-1-richard.henderson@linaro.org>


Richard Henderson (24):
  target/arm: Fix decode of align in VLDST_single
  target/arm: Add ALIGN_MEM to TBFLAG_ANY
  target/arm: Adjust gen_aa32_{ld,st}_i32 for align+endianness
  target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
  target/arm: Fix SCTLR_B test for TCGv_i64 load/store
  target/arm: Adjust gen_aa32_{ld,st}_i64 for align+endianness
  target/arm: Enforce word alignment for LDRD/STRD
  target/arm: Enforce alignment for LDA/LDAH/STL/STLH
  target/arm: Enforce alignment for LDM/STM
  target/arm: Enforce alignment for RFE
  target/arm: Enforce alignment for SRS
  target/arm: Enforce alignment for VLDM/VSTM
  target/arm: Enforce alignment for VLDR/VSTR
  target/arm: Enforce alignment for VLD1 (all lanes)
  target/arm: Enforce alignment for VLDn/VSTn (multiple)
  target/arm: Enforce alignment for VLDn/VSTn (single)
  target/arm: Use finalize_memop for aa64 gpr load/store
  target/arm: Use finalize_memop for aa64 fpr load/store
  target/arm: Enforce alignment for aa64 load-acq/store-rel
  target/arm: Use MemOp for size + endian in aa64 vector ld/st
  target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
  target/arm: Enforce alignment for aa64 vector LDn/STn (single)
  target/arm: Enforce alignment for sve LD1R
  target/arm: Enforce alignment for sve unpredicated LDR/STR

 target/arm/cpu.h                |  20 +--
 target/arm/translate.h          |  27 +++++
 target/arm/neon-ls.decode       |   4 +-
 target/arm/helper.c             |  19 ++-
 target/arm/translate-a64.c      | 175 ++++++++++++++-------------
 target/arm/translate-sve.c      |  60 ++++++---
 target/arm/translate.c          | 207 ++++++++++++++++++--------------
 target/arm/translate-neon.c.inc |  85 ++++++++++---
 target/arm/translate-vfp.c.inc  |  20 +--
 9 files changed, 391 insertions(+), 226 deletions(-)

-- 
2.25.1