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envelope-from=keithp@keithp.com; helo=elaine.keithp.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/26 17:06:21 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Keith Packard X-Patchwork-Original-From: Keith Packard via From: "Xingtao Yao \(Fujitsu\)\" via" This series first adapts the existing ARM semihosting code to be architecture-neutral, then adds RISC-V semihosting support using that. Patch 1/4 moves the ARM semihosting support code to common directories and adapts the build system to match. Patch 2/4 changes the public API to this code to use architecture-independent names and types. Patch 3/4 changes the internals of this code to use architecture neutral types where practical, and adds helper functions to abstract away the architecture-specific details. Patch 4/4 adds the RISC-V support, including modifying the breakpoint handling code to recognize a semihosting sequence and adding RISC-V specific implementations of the helper functions.