| Message ID | 20200930204604.20663-1-cupertinomiranda@gmail.com |
|---|---|
| Headers | show |
| Series | *** ARC port for review *** | expand |
Hi Cupertino, On 9/30/20 10:45 PM, cupertinomiranda@gmail.com wrote: > From: Cupertino Miranda <cmiranda@synopsys.com> > > Signed-off-by: Cupertino Miranda <cmiranda@synopsys.com> > --- ... > diff --git a/target/arc/Makefile.objs b/target/arc/Makefile.objs > new file mode 100644 > index 0000000000..7b2afd08e4 > --- /dev/null > +++ b/target/arc/Makefile.objs > @@ -0,0 +1,34 @@ > +# > +# QEMU ARC CPU > +# > +# Copyright (c) 2020 > +# > +# This library is free software; you can redistribute it and/or > +# modify it under the terms of the GNU Lesser General Public > +# License as published by the Free Software Foundation; either > +# version 2.1 of the License, or (at your option) any later version. > +# > +# This library is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > +# Lesser General Public License for more details. > +# > +# You should have received a copy of the GNU Lesser General Public > +# License along with this library; if not, see > +# <http://www.gnu.org/licenses/lgpl-2.1.html> > +# > + > +obj-y += translate.o > +obj-y += helper.o > +obj-y += cpu.o > +obj-y += op_helper.o > +obj-y += gdbstub.o > +obj-y += decoder.o > +obj-y += regs.o > +obj-y += semfunc.o > +obj-y += semfunc-helper.o > +obj-y += mmu.o > +obj-y += mpu.o > +obj-y += timer.o > +obj-y += irq.o > +obj-y += cache.o We don't use Makefiles anymore, and you already provides meson.build. > diff --git a/target/arc/arc-common.h b/target/arc/arc-common.h > new file mode 100644 > index 0000000000..8013e1d2ed > --- /dev/null > +++ b/target/arc/arc-common.h > @@ -0,0 +1,55 @@ > +/* > + * Common header file to be used by cpu and disassembler. > + * Copyright (C) 2017 Free Software Foundation, Inc. > + * > + * You should have received a copy of the GNU General Public License > + * along with GAS or GDB; see the file COPYING3. If not, write to > + * the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, > + * MA 02110-1301, USA. > + */ > + > +#ifndef ARC_COMMON_H > +#define ARC_COMMON_H > + > +#include "qemu/osdep.h" ... Do not include "qemu/osdep.h" in headers. > +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ > +/* vim: set ts=4 sw=4 et: */ > diff --git a/target/arc/cpu-qom.h b/target/arc/cpu-qom.h > new file mode 100644 > index 0000000000..413b693558 > --- /dev/null > +++ b/target/arc/cpu-qom.h > @@ -0,0 +1,53 @@ > +/* > + * QEMU ARC CPU > + * > + * Copyright (c) 2016 Michael Rolnik ??? > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * <http://www.gnu.org/licenses/lgpl-2.1.html> > + */ > + ... > diff --git a/target/arc/cpu.c b/target/arc/cpu.c > new file mode 100644 > index 0000000000..bbcb371760 > --- /dev/null > +++ b/target/arc/cpu.c > @@ -0,0 +1,468 @@ > +/* > + * QEMU ARC CPU > + * > + * Copyright (c) 2020 (c) Synopsys? > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * http://www.gnu.org/licenses/lgpl-2.1.html > + */ ... > +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ > +/* vim: set ts=4 sw=4 et: */ > diff --git a/target/arc/cpu.h b/target/arc/cpu.h > new file mode 100644 > index 0000000000..e8446366e5 > --- /dev/null > +++ b/target/arc/cpu.h > @@ -0,0 +1,532 @@ > + /* > + * QEMU ARC CPU > + * > + * Copyright (c) 2020 Again. > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * <http://www.gnu.org/licenses/lgpl-2.1.html> > + */ > + > +#ifndef CPU_ARC_H > +#define CPU_ARC_H > + ... > + > +/* > + * ArcCPU: > + * @env: #CPUMBState > + * > + * An ARC CPU. > + */ > +struct ARCCPU { > + /*< private >*/ > + CPUState parent_obj; > + > + /*< public >*/ > + > + /* ARC Configuration Settings. */ > + struct { > + uint32_t addr_size; > + bool aps_feature; > + bool byte_order; > + bool bitscan_option; > + uint32_t br_bc_entries; > + uint32_t br_pt_entries; > + bool br_bc_full_tag; > + uint8_t br_rs_entries; > + uint32_t br_bc_tag_size; > + uint8_t br_tosq_entries; > + uint8_t br_fb_entries; > + bool code_density; > + bool code_protect; > + uint8_t dccm_mem_cycles; > + bool dccm_posedge; > + uint8_t dccm_mem_bancks; > + uint8_t dc_mem_cycles; > + bool dc_posedge; > + bool dmp_unaligned; > + bool ecc_exception; > + uint32_t external_interrupts; > + uint8_t ecc_option; > + bool firq_option; > + bool fpu_dp_option; > + bool fpu_fma_option; > + bool fpu_div_option; > + bool has_actionpoints; > + bool has_fpu; > + bool has_interrupts; > + bool has_mmu; > + bool has_mpu; > + bool has_timer_0; > + bool has_timer_1; > + bool has_pct; > + bool has_rtt; > + bool has_smart; > + uint32_t intvbase_preset; > + uint32_t lpc_size; > + uint8_t mpu_num_regions; > + uint8_t mpy_option; > + uint32_t mmu_page_size_sel0; > + uint32_t mmu_page_size_sel1; > + uint32_t mmu_pae_enabled; > + uint32_t ntlb_num_entries; > + uint32_t num_actionpoints; > + uint32_t number_of_interrupts; > + uint32_t number_of_levels; > + uint32_t pct_counters; > + uint32_t pct_interrupt; > + uint32_t pc_size; > + uint32_t rgf_num_regs; Maybe use 'unsigned' for numbers (various uses). > + uint32_t rgf_banked_regs; > + uint32_t rgf_num_banks; > + bool rtc_option; > + uint32_t rtt_feature_level; > + bool stack_checking; > + bool swap_option; > + uint32_t smar_stack_entries; > + uint32_t smart_implementation; > + uint32_t stlb_num_entries; > + uint32_t slc_size; > + uint32_t slc_line_size; > + uint32_t slc_ways; > + uint32_t slc_tag_banks; > + uint32_t slc_tram_delay; > + uint32_t slc_dbank_width; > + uint32_t slc_data_banks; > + uint32_t slc_dram_delay; > + bool slc_mem_bus_width; > + uint32_t slc_ecc_option; > + bool slc_data_halfcycle_steal; > + bool slc_data_add_pre_pipeline; > + bool uaux_option; > + uint32_t freq_hz; /* CPU frequency in hz, needed for timers. */ > + } cfg; > + [...] Regards, Phil.
Hi Philippe, Thank you for your time reviewing our patches. My apologies for reacting to it so late. :-( Once we decided to make this port we noticed that Michael Rolnik had submitt a port for ARC700 to QEMU mailinglist. As we tested it, we decided to use his directory structure, and for that reason the most generic files as well, although significantly changing everything else. As a way to credit him for the initial work, we left his copyright header in that file. Maybe that should instead mention him in the commits, or in the cover letter instead. Please let me know of the proper way. Regarding "unsigned", some of these variables are used as "auxiliary registers" and should at least be 32bit. Some others might perfectly well be resized to "unsigned".We will certainly revisit these definitions to make sure we use the proper types for the case. Regards, Cupertino On Wed, Oct 7, 2020 at 5:09 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > Hi Cupertino, > > On 9/30/20 10:45 PM, cupertinomiranda@gmail.com wrote: > > From: Cupertino Miranda <cmiranda@synopsys.com> > > > > Signed-off-by: Cupertino Miranda <cmiranda@synopsys.com> > > --- > ... > > > diff --git a/target/arc/Makefile.objs b/target/arc/Makefile.objs > > new file mode 100644 > > index 0000000000..7b2afd08e4 > > --- /dev/null > > +++ b/target/arc/Makefile.objs > > @@ -0,0 +1,34 @@ > > +# > > +# QEMU ARC CPU > > +# > > +# Copyright (c) 2020 > > +# > > +# This library is free software; you can redistribute it and/or > > +# modify it under the terms of the GNU Lesser General Public > > +# License as published by the Free Software Foundation; either > > +# version 2.1 of the License, or (at your option) any later version. > > +# > > +# This library is distributed in the hope that it will be useful, > > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > +# Lesser General Public License for more details. > > +# > > +# You should have received a copy of the GNU Lesser General Public > > +# License along with this library; if not, see > > +# <http://www.gnu.org/licenses/lgpl-2.1.html> > > +# > > + > > +obj-y += translate.o > > +obj-y += helper.o > > +obj-y += cpu.o > > +obj-y += op_helper.o > > +obj-y += gdbstub.o > > +obj-y += decoder.o > > +obj-y += regs.o > > +obj-y += semfunc.o > > +obj-y += semfunc-helper.o > > +obj-y += mmu.o > > +obj-y += mpu.o > > +obj-y += timer.o > > +obj-y += irq.o > > +obj-y += cache.o > > We don't use Makefiles anymore, and you already provides meson.build. > > > diff --git a/target/arc/arc-common.h b/target/arc/arc-common.h > > new file mode 100644 > > index 0000000000..8013e1d2ed > > --- /dev/null > > +++ b/target/arc/arc-common.h > > @@ -0,0 +1,55 @@ > > +/* > > + * Common header file to be used by cpu and disassembler. > > + * Copyright (C) 2017 Free Software Foundation, Inc. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with GAS or GDB; see the file COPYING3. If not, write to > > + * the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, > > + * MA 02110-1301, USA. > > + */ > > + > > +#ifndef ARC_COMMON_H > > +#define ARC_COMMON_H > > + > > +#include "qemu/osdep.h" > ... > > Do not include "qemu/osdep.h" in headers. > > > +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ > > +/* vim: set ts=4 sw=4 et: */ > > diff --git a/target/arc/cpu-qom.h b/target/arc/cpu-qom.h > > new file mode 100644 > > index 0000000000..413b693558 > > --- /dev/null > > +++ b/target/arc/cpu-qom.h > > @@ -0,0 +1,53 @@ > > +/* > > + * QEMU ARC CPU > > + * > > + * Copyright (c) 2016 Michael Rolnik > > ??? > > > + * > > + * This library is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2.1 of the License, or (at your option) any later version. > > + * > > + * This library is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with this library; if not, see > > + * <http://www.gnu.org/licenses/lgpl-2.1.html> > > + */ > > + > ... > > > diff --git a/target/arc/cpu.c b/target/arc/cpu.c > > new file mode 100644 > > index 0000000000..bbcb371760 > > --- /dev/null > > +++ b/target/arc/cpu.c > > @@ -0,0 +1,468 @@ > > +/* > > + * QEMU ARC CPU > > + * > > + * Copyright (c) 2020 > > (c) Synopsys? > > > + * > > + * This library is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2.1 of the License, or (at your option) any later version. > > + * > > + * This library is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with this library; if not, see > > + * http://www.gnu.org/licenses/lgpl-2.1.html > > + */ > ... > > > +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ > > +/* vim: set ts=4 sw=4 et: */ > > diff --git a/target/arc/cpu.h b/target/arc/cpu.h > > new file mode 100644 > > index 0000000000..e8446366e5 > > --- /dev/null > > +++ b/target/arc/cpu.h > > @@ -0,0 +1,532 @@ > > + /* > > + * QEMU ARC CPU > > + * > > + * Copyright (c) 2020 > > Again. > > > + * > > + * This library is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2.1 of the License, or (at your option) any later version. > > + * > > + * This library is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with this library; if not, see > > + * <http://www.gnu.org/licenses/lgpl-2.1.html> > > + */ > > + > > +#ifndef CPU_ARC_H > > +#define CPU_ARC_H > > + > ... > > > + > > +/* > > + * ArcCPU: > > + * @env: #CPUMBState > > + * > > + * An ARC CPU. > > + */ > > +struct ARCCPU { > > + /*< private >*/ > > + CPUState parent_obj; > > + > > + /*< public >*/ > > + > > + /* ARC Configuration Settings. */ > > + struct { > > + uint32_t addr_size; > > + bool aps_feature; > > + bool byte_order; > > + bool bitscan_option; > > + uint32_t br_bc_entries; > > + uint32_t br_pt_entries; > > + bool br_bc_full_tag; > > + uint8_t br_rs_entries; > > + uint32_t br_bc_tag_size; > > + uint8_t br_tosq_entries; > > + uint8_t br_fb_entries; > > + bool code_density; > > + bool code_protect; > > + uint8_t dccm_mem_cycles; > > + bool dccm_posedge; > > + uint8_t dccm_mem_bancks; > > + uint8_t dc_mem_cycles; > > + bool dc_posedge; > > + bool dmp_unaligned; > > + bool ecc_exception; > > + uint32_t external_interrupts; > > + uint8_t ecc_option; > > + bool firq_option; > > + bool fpu_dp_option; > > + bool fpu_fma_option; > > + bool fpu_div_option; > > + bool has_actionpoints; > > + bool has_fpu; > > + bool has_interrupts; > > + bool has_mmu; > > + bool has_mpu; > > + bool has_timer_0; > > + bool has_timer_1; > > + bool has_pct; > > + bool has_rtt; > > + bool has_smart; > > + uint32_t intvbase_preset; > > + uint32_t lpc_size; > > + uint8_t mpu_num_regions; > > + uint8_t mpy_option; > > + uint32_t mmu_page_size_sel0; > > + uint32_t mmu_page_size_sel1; > > + uint32_t mmu_pae_enabled; > > + uint32_t ntlb_num_entries; > > + uint32_t num_actionpoints; > > + uint32_t number_of_interrupts; > > + uint32_t number_of_levels; > > + uint32_t pct_counters; > > + uint32_t pct_interrupt; > > + uint32_t pc_size; > > + uint32_t rgf_num_regs; > > Maybe use 'unsigned' for numbers (various uses). > > > + uint32_t rgf_banked_regs; > > + uint32_t rgf_num_banks; > > + bool rtc_option; > > + uint32_t rtt_feature_level; > > + bool stack_checking; > > + bool swap_option; > > + uint32_t smar_stack_entries; > > + uint32_t smart_implementation; > > + uint32_t stlb_num_entries; > > + uint32_t slc_size; > > + uint32_t slc_line_size; > > + uint32_t slc_ways; > > + uint32_t slc_tag_banks; > > + uint32_t slc_tram_delay; > > + uint32_t slc_dbank_width; > > + uint32_t slc_data_banks; > > + uint32_t slc_dram_delay; > > + bool slc_mem_bus_width; > > + uint32_t slc_ecc_option; > > + bool slc_data_halfcycle_steal; > > + bool slc_data_add_pre_pipeline; > > + bool uaux_option; > > + uint32_t freq_hz; /* CPU frequency in hz, needed for timers. */ > > + } cfg; > > + > [...] > Regards, > > Phil.
Hi Philippe, On Wed, Oct 7, 2020 at 5:31 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > Hi Cupertino, Claudiu, > > On 9/30/20 10:46 PM, cupertinomiranda@gmail.com wrote: > > From: Claudiu Zissulescu <claziss@synopsys.com> > > > > Add the Synopsys ARC boards, arc_sim for testing, sim-hs main emulation > > board using standard UART and nsim which includes a Synopsys ARC specific > > UART implementation. > > > > Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> > > --- > > hw/arc/Makefile.objs | 21 +++ > > hw/arc/arc_sim.c | 143 ++++++++++++++++++++ > > hw/arc/arc_uart.c | 267 ++++++++++++++++++++++++++++++++++++++ > > hw/arc/board-hsdk.c | 107 +++++++++++++++ > > hw/arc/boot.c | 95 ++++++++++++++ > > hw/arc/boot.h | 21 +++ > > hw/arc/meson.build | 13 ++ > > hw/arc/nsim.c | 86 ++++++++++++ > > hw/arc/pic_cpu.c | 111 ++++++++++++++++ > > hw/arc/sample.c | 77 +++++++++++ > > hw/arc/sim-hs.c | 107 +++++++++++++++ > > include/hw/arc/arc_uart.h | 43 ++++++ > > include/hw/arc/cpudevs.h | 10 ++ > > 13 files changed, 1101 insertions(+) > > create mode 100644 hw/arc/Makefile.objs > > create mode 100644 hw/arc/arc_sim.c > > create mode 100644 hw/arc/arc_uart.c > > create mode 100644 hw/arc/board-hsdk.c > > create mode 100644 hw/arc/boot.c > > create mode 100644 hw/arc/boot.h > > create mode 100644 hw/arc/meson.build > > create mode 100644 hw/arc/nsim.c > > create mode 100644 hw/arc/pic_cpu.c > > create mode 100644 hw/arc/sample.c > > create mode 100644 hw/arc/sim-hs.c > > create mode 100644 include/hw/arc/arc_uart.h > > create mode 100644 include/hw/arc/cpudevs.h > > Please split in various commits: > > - hw/char/arc_uart > - hw/intc/synopsys_pic or something > - hw/arc/boot > - hw/arc/*sim* > - hw/arc/*hsdk* > > (Also it would simplify differentiating the architectural > part of your patches from the hardware ones if you use the > target/arc/ prefix in your previous patches). Got it, will make it happen in the next submission. > > > > > diff --git a/hw/arc/Makefile.objs b/hw/arc/Makefile.objs > > new file mode 100644 > > index 0000000000..28d7766cd9 > > --- /dev/null > > +++ b/hw/arc/Makefile.objs > > @@ -0,0 +1,21 @@ > > +# > > +# QEMU ARC CPU > > +# > > +# Copyright (c) 2019 > > +# > > +# This library is free software; you can redistribute it and/or > > +# modify it under the terms of the GNU Lesser General Public > > +# License as published by the Free Software Foundation; either > > +# version 2.1 of the License, or (at your option) any later version. > > +# > > +# This library is distributed in the hope that it will be useful, > > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > +# Lesser General Public License for more details. > > +# > > +# You should have received a copy of the GNU Lesser General Public > > +# License along with this library; if not, see > > +# http://www.gnu.org/licenses/lgpl-2.1.html > > +# > > + > > +obj-y = arc_sim.o arc_uart.o sample.o pic_cpu.o boot.o board-hsdk.o sim-hs.o nsim.o > > We don't use Makefile anymore. Oups, sorry for that, we had just rebased older code ... need to remove those. > > > diff --git a/hw/arc/arc_sim.c b/hw/arc/arc_sim.c > > new file mode 100644 > > index 0000000000..8020a03d85 > > --- /dev/null > > +++ b/hw/arc/arc_sim.c > > @@ -0,0 +1,143 @@ > > +/* > > + * This library is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2 of the License, or (at your option) any later version. > > + * > > + * This library is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with this library; if not, see <http://www.gnu.org/licenses/>. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qapi/error.h" > > +#include "cpu.h" > > +#include "hw/hw.h" > > +#include "hw/boards.h" > > +#include "elf.h" > > +#include "hw/char/serial.h" > > +#include "net/net.h" > > +#include "hw/loader.h" > > +#include "exec/memory.h" > > +#include "exec/address-spaces.h" > > +#include "sysemu/reset.h" > > +#include "sysemu/runstate.h" > > +#include "sysemu/sysemu.h" > > +#include "hw/sysbus.h" > > +#include "hw/arc/cpudevs.h" > > +#include "boot.h" > > + > > +static void arc_sim_net_init(MemoryRegion *address_space, > > + hwaddr base, > > + hwaddr descriptors, > > + qemu_irq irq, NICInfo *nd) > > +{ > > + DeviceState *dev; > > + SysBusDevice *s; > > + > > + dev = qdev_new("open_eth"); > > + qdev_set_nic_properties(dev, nd); > > + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > > + > > + s = SYS_BUS_DEVICE(dev); > > + sysbus_connect_irq(s, 0, irq); > > + memory_region_add_subregion(address_space, base, > > + sysbus_mmio_get_region(s, 0)); > > + memory_region_add_subregion(address_space, descriptors, > > + sysbus_mmio_get_region(s, 1)); > > +} > > + > > +static uint64_t arc_io_read(void *opaque, hwaddr addr, unsigned size) > > +{ > > + return 0; > > +} > > + > > +static void arc_io_write(void *opaque, hwaddr addr, > > + uint64_t val, unsigned size) > > +{ > > + switch (addr) { > > + case 0x08: /* board reset. */ > > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); > > + break; > > + default: > > + break; > > + } > > +} > > + > > +static const MemoryRegionOps arc_io_ops = { > > + .read = arc_io_read, > > + .write = arc_io_write, > > + .endianness = DEVICE_NATIVE_ENDIAN, > > +}; > > + > > +static void arc_sim_init(MachineState *machine) > > +{ > > + static struct arc_boot_info boot_info; > > + unsigned int smp_cpus = machine->smp.cpus; > > + ram_addr_t ram_base = 0; > > + ram_addr_t ram_size = machine->ram_size; > > + ARCCPU *cpu = NULL; > > + MemoryRegion *ram, *system_io; > > + int n; > > + > > + boot_info.ram_start = ram_base; > > + boot_info.ram_size = ram_size; > > + boot_info.kernel_filename = machine->kernel_filename; > > + > > + for (n = 0; n < smp_cpus; n++) { > > + cpu = ARC_CPU(object_new(machine->cpu_type)); > > + if (cpu == NULL) { > > + fprintf(stderr, "Unable to find CPU definition!\n"); > > + exit(1); > > + } > > + > > + /* Set the initial CPU properties. */ > > + object_property_set_uint(OBJECT(cpu), "freq_hz", 1000000, &error_fatal); > > + object_property_set_bool(OBJECT(cpu), "rtc-opt", true, &error_fatal); > > + object_property_set_bool(OBJECT(cpu), "realized", true, &error_fatal); > > + > > + /* Initialize internal devices. */ > > + cpu_arc_pic_init(cpu); > > + cpu_arc_clock_init(cpu); > > + > > + qemu_register_reset(arc_cpu_reset, cpu); > > + } > > + > > + ram = g_new(MemoryRegion, 1); > > + memory_region_init_ram(ram, NULL, "arc.ram", ram_size, &error_fatal); > > + memory_region_add_subregion(get_system_memory(), ram_base, ram); > > + > > + system_io = g_new(MemoryRegion, 1); > > + memory_region_init_io(system_io, NULL, &arc_io_ops, NULL, "arc.io", > > + 1024); > > + memory_region_add_subregion(get_system_memory(), 0xf0000000, system_io); > > + > > + serial_mm_init(get_system_memory(), 0x90000000, 2, cpu->env.irq[20], > > + 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); > > + > > + if (nd_table[0].used) { > > + arc_sim_net_init(get_system_memory(), 0x92000000, > > + 0x92000400, cpu->env.irq[4], nd_table); > > + } > > + > > + arc_load_kernel(cpu, &boot_info); > > +} > > + > > +static void arc_sim_machine_init(MachineClass *mc) > > +{ > > + mc->desc = "ARCxx simulation"; > > + mc->init = arc_sim_init; > > + mc->max_cpus = 1; > > + mc->is_default = false; > > + mc->default_cpu_type = ARC_CPU_TYPE_NAME("archs"); > > +} > > + > > +DEFINE_MACHINE("arc-sim", arc_sim_machine_init) > > Can you share the link to the documentation of this simulator please? > I couldn't find it on the link you provided in the cover > (https://www.synopsys.com/designware-ip/processor-solutions.html) > and https://www.synopsys.com/dw/ipdir.php?ds=sim_nSIM doesn't > seem relevant. The free version of this simulator is in: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi Documentation is packed in that download. I am not aware of any location that would contain documentation for this. In any case, we believe that we will not need any nSIM board, and we would like to remove both the nsim board and the ARC UART implementation. There is no real benefit, as the support for ARC UART is being phased out even on nSIM simulator and it does not make sense to include it now in QEMU. We only implemented ARC UART since initially nSIM did not support generic UART, and we wanted to execute the same binaries on both nSIM and QEMU. At this point sim-hs board is doing precisely that. In any case we want to rename it to something more meaningful. > > > diff --git a/hw/arc/sample.c b/hw/arc/sample.c > > new file mode 100644 > > index 0000000000..0ecc11cf15 > > --- /dev/null > > +++ b/hw/arc/sample.c > > @@ -0,0 +1,77 @@ > > +/* > > + * QEMU ARC CPU > > + * > > + * Copyright (c) 2016 Michael Rolnik > > + * > > + * This library is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2.1 of the License, or (at your option) any later version. > > + * > > + * This library is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with this library; if not, see > > + * http://www.gnu.org/licenses/lgpl-2.1.html > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qapi/error.h" > > +#include "qemu-common.h" > > +#include "cpu.h" > > +#include "hw/hw.h" > > +#include "sysemu/sysemu.h" > > +#include "sysemu/qtest.h" > > +#include "ui/console.h" > > +#include "hw/boards.h" > > +#include "hw/loader.h" > > +#include "qemu/error-report.h" > > +#include "exec/address-spaces.h" > > +#include "include/hw/sysbus.h" > > + > > +#define SIZE_RAM 0x00020000 > > + > > +static void sample_init(MachineState *machine) > > +{ > > + MemoryRegion *ram; > > + > > + ARCCPU *cpu_arc ATTRIBUTE_UNUSED; > > + > > + ram = g_new(MemoryRegion, 1); > > + > > + cpu_arc = ARC_CPU(cpu_create("archs-" TYPE_ARC_CPU)); > > + > > + memory_region_init_ram(ram, NULL, "ram", SIZE_RAM, &error_fatal); > > + memory_region_add_subregion(get_system_memory(), PHYS_BASE_RAM, ram); > > + > > + char const *firmware = NULL; > > + char const *filename; > > + > > + if (machine->firmware) { > > + firmware = machine->firmware; > > + } > > + > > + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware); > > + if (!filename) { > > + error_report("Could not find flash image file '%s'", firmware); > > + exit(1); > > + } > > + > > + load_image_targphys(filename, PHYS_BASE_RAM + 0x100, SIZE_RAM); > > +} > > + > > +static void sample_machine_init(MachineClass *mc) > > +{ > > + mc->desc = "ARC sample/example board"; > > + mc->init = sample_init; > > + mc->is_default = false; > > +} > > + > > +DEFINE_MACHINE("sample", sample_machine_init) > > You don't need a "sample" board, you can use the "none" machine instead. Ok, will remove. > > Regards, > > Phil. Regards, Cupertino
From: Cupertino Miranda <cmiranda@synopsys.com> Hello everyone, It is with utmost pleasure that on behalf of Synopsys I initiate the upstream process for our ARCv2 architecture QEMU port. I am one of the main contributors to this port and member of the Synopsys GNU toolchain team, together with Claudiu Zissulescu and Shahab Vahedi. ARCv2 processors use RISC, and employ the 16-/32-bit instruction set architecture (ISA). ARC processors are configurable and extensible for a wide range of uses in system on a chip (SoC) devices. It is a common processor in deeply embedded systems, used in storage, digital home, mobile, automotive, and Internet of Things (IoT) applications. To facilitate reviewing, we split the files through several commits, attempting to keep file size to reviewable chunks. The port as presented implements the system softmmu hardware emulation, capable to boot and run Linux kernel. It has also been integrated as a patch in Zephyr project, where it is being used. To validate and guarantee correctness of the port through development, we have created TCG tests from the very beggining, covering the most fundamental CPU features. For the remaining instructions we validate the port through compiler testsuites, like DejaGNU, comparing results with real hardware executions. Would like also to thank our colleagues Vineet Gupta and Alexey Broadkin for their contributions, which due to the collapse of the development commits, got their contributions overcast by major ones. Link for Synopsys ARC processor page: - https://www.synopsys.com/designware-ip/processor-solutions.html ARC PRM for both HS and EM processors can be found in: - https://www.synopsys.com/dw/doc.php/ds/cc/programmers-reference-manual-ARC-EM.pdf - https://www.synopsys.com/dw/doc.php/ds/cc/programmers-reference-manual-ARC-HS.pdf. Looking forward to your comments and suggestions. Best regards, Cupertino Miranda *** BLURB HERE *** Claudiu Zissulescu (5): arc: Decoder code arc: Opcode definitions table arc: Add IRQ and timer subsystem support arc: Add Synopsys ARC emulation boards tests/tcg: ARC: Add TCG instruction definition tests Cupertino Miranda (5): arc: Add initial core cpu files arc: TCG and decoder glue code and helpers arc: TCG instruction definitions arc: Add BCR and AUX registers implementation arc: Add memory management unit (MMU) support Shahab Vahedi (4): arc: TCG instruction generator and hand-definitions arc: Add memory protection unit (MPU) support arc: Add gdbstub and XML for debugging support arc: Add support for ARCv2 configure | 5 + default-configs/arc-softmmu.mak | 5 + disas.c | 2 + disas/arc.c | 460 + disas/meson.build | 1 + gdb-xml/arc-aux-minimal.xml | 32 + gdb-xml/arc-aux-other.xml | 235 + gdb-xml/arc-core-v2.xml | 45 + hw/arc/Makefile.objs | 21 + hw/arc/arc_sim.c | 143 + hw/arc/arc_uart.c | 267 + hw/arc/board-hsdk.c | 107 + hw/arc/boot.c | 95 + hw/arc/boot.h | 21 + hw/arc/meson.build | 13 + hw/arc/nsim.c | 86 + hw/arc/pic_cpu.c | 111 + hw/arc/sample.c | 77 + hw/arc/sim-hs.c | 107 + hw/meson.build | 1 + include/disas/dis-asm.h | 10 +- include/elf.h | 3 + include/exec/poison.h | 2 + include/hw/arc/arc_uart.h | 43 + include/hw/arc/cpudevs.h | 10 + include/sysemu/arch_init.h | 1 + meson.build | 3 +- softmmu/arch_init.c | 2 + target/arc/Makefile.objs | 34 + target/arc/arc-common.h | 55 + target/arc/cache.c | 180 + target/arc/cache.h | 42 + target/arc/cpu-param.h | 20 + target/arc/cpu-qom.h | 53 + target/arc/cpu.c | 468 + target/arc/cpu.h | 532 + target/arc/decoder.c | 1276 ++ target/arc/decoder.h | 350 + target/arc/extra_mapping.def | 40 + target/arc/flags.def | 85 + target/arc/gdbstub.c | 421 + target/arc/helper.c | 293 + target/arc/helper.h | 46 + target/arc/internals.h | 37 + target/arc/irq.c | 658 + target/arc/irq.h | 37 + target/arc/meson.build | 20 + target/arc/mmu.c | 775 + target/arc/mmu.h | 165 + target/arc/mpu.c | 653 + target/arc/mpu.h | 140 + target/arc/op_helper.c | 749 + target/arc/opcodes.def | 19976 ++++++++++++++++++++++++ target/arc/operands.def | 123 + target/arc/regs-detail.def | 542 + target/arc/regs.c | 139 + target/arc/regs.def | 399 + target/arc/regs.h | 118 + target/arc/semfunc-helper.c | 492 + target/arc/semfunc-helper.h | 280 + target/arc/semfunc.c | 8474 ++++++++++ target/arc/semfunc.h | 61 + target/arc/semfunc_mapping.def | 329 + target/arc/timer.c | 456 + target/arc/timer.h | 32 + target/arc/translate.c | 1344 ++ target/arc/translate.h | 202 + target/meson.build | 1 + tests/Makefile.include | 1 + tests/tcg/Makefile.qemu | 16 +- tests/tcg/Makefile.target | 9 +- tests/tcg/arc/Makefile | 112 + tests/tcg/arc/Makefile.softmmu-target | 36 + tests/tcg/arc/Makefile.target | 101 + tests/tcg/arc/check_add.S | 11 + tests/tcg/arc/check_addx.S | 71 + tests/tcg/arc/check_andx.S | 36 + tests/tcg/arc/check_aslx.S | 57 + tests/tcg/arc/check_asrx.S | 86 + tests/tcg/arc/check_basic1.S | 30 + tests/tcg/arc/check_basic2.S | 26 + tests/tcg/arc/check_beq.S | 14 + tests/tcg/arc/check_beqx.S | 26 + tests/tcg/arc/check_big_tb.S | 173 + tests/tcg/arc/check_bnex.S | 26 + tests/tcg/arc/check_breqx.S | 26 + tests/tcg/arc/check_brgex.S | 26 + tests/tcg/arc/check_brhsx.S | 27 + tests/tcg/arc/check_brlox.S | 26 + tests/tcg/arc/check_brltx.S | 26 + tests/tcg/arc/check_brnex.S | 26 + tests/tcg/arc/check_bta.S | 294 + tests/tcg/arc/check_carry.S | 15 + tests/tcg/arc/check_enter_leave.S | 715 + tests/tcg/arc/check_excp.S | 17 + tests/tcg/arc/check_excp_1.c | 15 + tests/tcg/arc/check_excp_jumpdl_mmu.S | 44 + tests/tcg/arc/check_excp_mmu.S | 69 + tests/tcg/arc/check_flags.S | 23 + tests/tcg/arc/check_ldaw_mmu.S | 71 + tests/tcg/arc/check_ldstx.S | 37 + tests/tcg/arc/check_lp.S | 12 + tests/tcg/arc/check_lp02.S | 72 + tests/tcg/arc/check_lp03.S | 49 + tests/tcg/arc/check_lp04.S | 48 + tests/tcg/arc/check_lp05.S | 23 + tests/tcg/arc/check_lp06.S | 163 + tests/tcg/arc/check_lsrx.S | 33 + tests/tcg/arc/check_mac.S | 228 + tests/tcg/arc/check_manip_10_mmu.S | 173 + tests/tcg/arc/check_manip_4_mmu.S | 158 + tests/tcg/arc/check_manip_5_mmu.S | 166 + tests/tcg/arc/check_manip_mmu.S | 565 + tests/tcg/arc/check_mmu.S | 59 + tests/tcg/arc/check_mpu.S | 703 + tests/tcg/arc/check_mpyd.S | 543 + tests/tcg/arc/check_mpyw.S | 41 + tests/tcg/arc/check_norm.S | 40 + tests/tcg/arc/check_orx.S | 34 + tests/tcg/arc/check_prefetch.S | 37 + tests/tcg/arc/check_rolx.S | 47 + tests/tcg/arc/check_rorx.S | 64 + tests/tcg/arc/check_rtc.S | 29 + tests/tcg/arc/check_rtie_user.S | 30 + tests/tcg/arc/check_stld.S | 10 + tests/tcg/arc/check_subf.S | 67 + tests/tcg/arc/check_subx.S | 43 + tests/tcg/arc/check_swi.S | 115 + tests/tcg/arc/check_swirq.S | 27 + tests/tcg/arc/check_swirq1.S | 31 + tests/tcg/arc/check_swirq3.S | 49 + tests/tcg/arc/check_t01.S | 12 + tests/tcg/arc/check_t02.S | 9 + tests/tcg/arc/check_timer0.S | 36 + tests/tcg/arc/check_timer0_loop.S | 34 + tests/tcg/arc/check_timer0_loop3.S | 46 + tests/tcg/arc/check_timer0_retrig.S | 29 + tests/tcg/arc/check_timer0_sleep.S | 33 + tests/tcg/arc/check_timerX_freq.S | 87 + tests/tcg/arc/check_vadd.S | 510 + tests/tcg/arc/check_vsub.S | 510 + tests/tcg/arc/check_xorx.S | 32 + tests/tcg/arc/ivt.S | 38 + tests/tcg/arc/macros.inc | 261 + tests/tcg/arc/memory.x | 12 + tests/tcg/arc/mmu.inc | 132 + tests/tcg/arc/mpu.inc | 269 + tests/tcg/arc/tarc.ld | 15 + tests/tcg/arc/tarc_mmu.ld | 15 + tests/tcg/arc/test_macros.h | 257 + tests/tcg/configure.sh | 3 +- 151 files changed, 50283 insertions(+), 9 deletions(-) create mode 100644 default-configs/arc-softmmu.mak create mode 100644 disas/arc.c create mode 100644 gdb-xml/arc-aux-minimal.xml create mode 100644 gdb-xml/arc-aux-other.xml create mode 100644 gdb-xml/arc-core-v2.xml create mode 100644 hw/arc/Makefile.objs create mode 100644 hw/arc/arc_sim.c create mode 100644 hw/arc/arc_uart.c create mode 100644 hw/arc/board-hsdk.c create mode 100644 hw/arc/boot.c create mode 100644 hw/arc/boot.h create mode 100644 hw/arc/meson.build create mode 100644 hw/arc/nsim.c create mode 100644 hw/arc/pic_cpu.c create mode 100644 hw/arc/sample.c create mode 100644 hw/arc/sim-hs.c create mode 100644 include/hw/arc/arc_uart.h create mode 100644 include/hw/arc/cpudevs.h create mode 100644 target/arc/Makefile.objs create mode 100644 target/arc/arc-common.h create mode 100644 target/arc/cache.c create mode 100644 target/arc/cache.h create mode 100644 target/arc/cpu-param.h create mode 100644 target/arc/cpu-qom.h create mode 100644 target/arc/cpu.c create mode 100644 target/arc/cpu.h create mode 100644 target/arc/decoder.c create mode 100644 target/arc/decoder.h create mode 100644 target/arc/extra_mapping.def create mode 100644 target/arc/flags.def create mode 100644 target/arc/gdbstub.c create mode 100644 target/arc/helper.c create mode 100644 target/arc/helper.h create mode 100644 target/arc/internals.h create mode 100644 target/arc/irq.c create mode 100644 target/arc/irq.h create mode 100644 target/arc/meson.build create mode 100644 target/arc/mmu.c create mode 100644 target/arc/mmu.h create mode 100644 target/arc/mpu.c create mode 100644 target/arc/mpu.h create mode 100644 target/arc/op_helper.c create mode 100644 target/arc/opcodes.def create mode 100644 target/arc/operands.def create mode 100644 target/arc/regs-detail.def create mode 100644 target/arc/regs.c create mode 100644 target/arc/regs.def create mode 100644 target/arc/regs.h create mode 100644 target/arc/semfunc-helper.c create mode 100644 target/arc/semfunc-helper.h create mode 100644 target/arc/semfunc.c create mode 100644 target/arc/semfunc.h create mode 100644 target/arc/semfunc_mapping.def create mode 100644 target/arc/timer.c create mode 100644 target/arc/timer.h create mode 100644 target/arc/translate.c create mode 100644 target/arc/translate.h create mode 100644 tests/tcg/arc/Makefile create mode 100644 tests/tcg/arc/Makefile.softmmu-target create mode 100644 tests/tcg/arc/Makefile.target create mode 100644 tests/tcg/arc/check_add.S create mode 100644 tests/tcg/arc/check_addx.S create mode 100644 tests/tcg/arc/check_andx.S create mode 100644 tests/tcg/arc/check_aslx.S create mode 100644 tests/tcg/arc/check_asrx.S create mode 100644 tests/tcg/arc/check_basic1.S create mode 100644 tests/tcg/arc/check_basic2.S create mode 100644 tests/tcg/arc/check_beq.S create mode 100644 tests/tcg/arc/check_beqx.S create mode 100644 tests/tcg/arc/check_big_tb.S create mode 100644 tests/tcg/arc/check_bnex.S create mode 100644 tests/tcg/arc/check_breqx.S create mode 100644 tests/tcg/arc/check_brgex.S create mode 100644 tests/tcg/arc/check_brhsx.S create mode 100644 tests/tcg/arc/check_brlox.S create mode 100644 tests/tcg/arc/check_brltx.S create mode 100644 tests/tcg/arc/check_brnex.S create mode 100644 tests/tcg/arc/check_bta.S create mode 100644 tests/tcg/arc/check_carry.S create mode 100644 tests/tcg/arc/check_enter_leave.S create mode 100644 tests/tcg/arc/check_excp.S create mode 100644 tests/tcg/arc/check_excp_1.c create mode 100644 tests/tcg/arc/check_excp_jumpdl_mmu.S create mode 100644 tests/tcg/arc/check_excp_mmu.S create mode 100644 tests/tcg/arc/check_flags.S create mode 100644 tests/tcg/arc/check_ldaw_mmu.S create mode 100644 tests/tcg/arc/check_ldstx.S create mode 100644 tests/tcg/arc/check_lp.S create mode 100644 tests/tcg/arc/check_lp02.S create mode 100644 tests/tcg/arc/check_lp03.S create mode 100644 tests/tcg/arc/check_lp04.S create mode 100644 tests/tcg/arc/check_lp05.S create mode 100644 tests/tcg/arc/check_lp06.S create mode 100644 tests/tcg/arc/check_lsrx.S create mode 100644 tests/tcg/arc/check_mac.S create mode 100644 tests/tcg/arc/check_manip_10_mmu.S create mode 100644 tests/tcg/arc/check_manip_4_mmu.S create mode 100644 tests/tcg/arc/check_manip_5_mmu.S create mode 100644 tests/tcg/arc/check_manip_mmu.S create mode 100644 tests/tcg/arc/check_mmu.S create mode 100644 tests/tcg/arc/check_mpu.S create mode 100644 tests/tcg/arc/check_mpyd.S create mode 100644 tests/tcg/arc/check_mpyw.S create mode 100644 tests/tcg/arc/check_norm.S create mode 100644 tests/tcg/arc/check_orx.S create mode 100644 tests/tcg/arc/check_prefetch.S create mode 100644 tests/tcg/arc/check_rolx.S create mode 100644 tests/tcg/arc/check_rorx.S create mode 100644 tests/tcg/arc/check_rtc.S create mode 100644 tests/tcg/arc/check_rtie_user.S create mode 100644 tests/tcg/arc/check_stld.S create mode 100644 tests/tcg/arc/check_subf.S create mode 100644 tests/tcg/arc/check_subx.S create mode 100644 tests/tcg/arc/check_swi.S create mode 100644 tests/tcg/arc/check_swirq.S create mode 100644 tests/tcg/arc/check_swirq1.S create mode 100644 tests/tcg/arc/check_swirq3.S create mode 100644 tests/tcg/arc/check_t01.S create mode 100644 tests/tcg/arc/check_t02.S create mode 100644 tests/tcg/arc/check_timer0.S create mode 100644 tests/tcg/arc/check_timer0_loop.S create mode 100644 tests/tcg/arc/check_timer0_loop3.S create mode 100644 tests/tcg/arc/check_timer0_retrig.S create mode 100644 tests/tcg/arc/check_timer0_sleep.S create mode 100644 tests/tcg/arc/check_timerX_freq.S create mode 100644 tests/tcg/arc/check_vadd.S create mode 100644 tests/tcg/arc/check_vsub.S create mode 100644 tests/tcg/arc/check_xorx.S create mode 100644 tests/tcg/arc/ivt.S create mode 100644 tests/tcg/arc/macros.inc create mode 100644 tests/tcg/arc/memory.x create mode 100644 tests/tcg/arc/mmu.inc create mode 100644 tests/tcg/arc/mpu.inc create mode 100644 tests/tcg/arc/tarc.ld create mode 100644 tests/tcg/arc/tarc_mmu.ld create mode 100644 tests/tcg/arc/test_macros.h