| Message ID | 20200929190448.31116-1-frank.chang@sifive.com |
|---|---|
| Headers | show |
| Series | support vector extension v1.0 | expand |
On Wed, Sep 30, 2020 at 3:04 AM <frank.chang@sifive.com> wrote: > From: Frank Chang <frank.chang@sifive.com> > > This patchset implements the vector extension v1.0 for RISC-V on QEMU. > > This patchset is sent as RFC because RVV v1.0 is still in draft state. > v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset. > > The port is available here: > https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v5 > > You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0) > to run with RVV v1.0 instructions. > > Note: This patchset depends on two other patchsets listed in Based-on > section below so it might not able to be built unless those two > patchsets are applied. > > Changelog: > > v5 > * refactor RVV v1.0 check functions. > (Thanks to Richard Henderson's bitwise tricks.) > * relax RV_VLEN_MAX to 1024-bits. > * implement vstart CSR's behaviors. > * trigger illegal instruction exception if frm is not valid for > vector floating-point instructions. > * rebase on riscv-to-apply.next. > > v4 > * remove explicit float flmul variable in DisasContext. > * replace floating-point calculations with shift operations to > improve performance. > * relax RV_VLEN_MAX to 512-bits. > > v3 > * apply nan-box helpers from Richard Henderson. > * remove fp16 api changes as they are sent independently in another > pathcset by Chih-Min Chao. > * remove all tail elements clear functions as tail elements can > retain unchanged for either VTA set to undisturbed or agnostic. > * add fp16 nan-box check generator function. > * add floating-point rounding mode enum. > * replace flmul arithmetic with shifts to avoid floating-point > conversions. > * add Zvqmac extension. > * replace gdbstub vector register xml files with dynamic generator. > * bumped to RVV v1.0. > * RVV v1.0 related changes: > * add vl<nf>re<eew>.v and vs<nf>r.v vector whole register > load/store instructions > * add vrgatherei16 instruction. > * rearranged bits in vtype to make vlmul bits into a contiguous > field. > > v2 > * drop v0.7.1 support. > * replace invisible return check macros with functions. > * move mark_vs_dirty() to translators. > * add SSTATUS_VS flag for s-mode. > * nan-box scalar fp register for floating-point operations. > * add gdbstub files for vector registers to allow system-mode > debugging with GDB. > > Based-on: <20200909001647.532249-1-richard.henderson@linaro.org/> > Based-on: <1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/> > > Frank Chang (62): > target/riscv: drop vector 0.7.1 and add 1.0 support > target/riscv: Use FIELD_EX32() to extract wd field > target/riscv: rvv-1.0: introduce writable misa.v field > target/riscv: rvv-1.0: add translation-time vector context status > target/riscv: rvv-1.0: remove rvv related codes from fcsr registers > target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr > registers > target/riscv: rvv-1.0: remove MLEN calculations > target/riscv: rvv-1.0: add fractional LMUL > target/riscv: rvv-1.0: add VMA and VTA > target/riscv: rvv-1.0: update check functions > target/riscv: introduce more imm value modes in translator functions > target/riscv: rvv:1.0: add translation-time nan-box helper function > target/riscv: rvv-1.0: configure instructions > target/riscv: rvv-1.0: stride load and store instructions > target/riscv: rvv-1.0: index load and store instructions > target/riscv: rvv-1.0: fix address index overflow bug of indexed > load/store insns > target/riscv: rvv-1.0: fault-only-first unit stride load > target/riscv: rvv-1.0: amo operations > target/riscv: rvv-1.0: load/store whole register instructions > target/riscv: rvv-1.0: update vext_max_elems() for load/store insns > target/riscv: rvv-1.0: take fractional LMUL into vector max elements > calculation > target/riscv: rvv-1.0: floating-point square-root instruction > target/riscv: rvv-1.0: floating-point classify instructions > target/riscv: rvv-1.0: mask population count instruction > target/riscv: rvv-1.0: find-first-set mask bit instruction > target/riscv: rvv-1.0: set-X-first mask bit instructions > target/riscv: rvv-1.0: iota instruction > target/riscv: rvv-1.0: element index instruction > target/riscv: rvv-1.0: allow load element with sign-extended > target/riscv: rvv-1.0: register gather instructions > target/riscv: rvv-1.0: integer scalar move instructions > target/riscv: rvv-1.0: floating-point move instruction > target/riscv: rvv-1.0: floating-point scalar move instructions > target/riscv: rvv-1.0: whole register move instructions > target/riscv: rvv-1.0: integer extension instructions > target/riscv: rvv-1.0: single-width averaging add and subtract > instructions > target/riscv: rvv-1.0: single-width bit shift instructions > target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow > target/riscv: rvv-1.0: narrowing integer right shift instructions > target/riscv: rvv-1.0: widening integer multiply-add instructions > target/riscv: rvv-1.0: single-width saturating add and subtract > instructions > target/riscv: rvv-1.0: integer comparison instructions > target/riscv: rvv-1.0: floating-point compare instructions > target/riscv: rvv-1.0: mask-register logical instructions > target/riscv: rvv-1.0: slide instructions > target/riscv: rvv-1.0: floating-point slide instructions > target/riscv: rvv-1.0: narrowing fixed-point clip instructions > target/riscv: rvv-1.0: single-width floating-point reduction > target/riscv: rvv-1.0: widening floating-point reduction instructions > target/riscv: rvv-1.0: single-width scaling shift instructions > target/riscv: rvv-1.0: remove widening saturating scaled multiply-add > target/riscv: rvv-1.0: remove vmford.vv and vmford.vf > target/riscv: rvv-1.0: remove integer extract instruction > target/riscv: rvv-1.0: floating-point min/max instructions > target/riscv: introduce floating-point rounding mode enum > target/riscv: rvv-1.0: floating-point/integer type-convert > instructions > target/riscv: rvv-1.0: widening floating-point/integer type-convert > target/riscv: add "set round to odd" rounding mode helper function > target/riscv: rvv-1.0: narrowing floating-point/integer type-convert > target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits > target/riscv: implement vstart CSR > target/riscv: trigger illegal instruction exception if frm is not > valid > > Greentime Hu (1): > target/riscv: rvv-1.0: add vlenb register > > Hsiangkai Wang (2): > target/riscv: gdb: modify gdb csr xml file to align with csr register > map > target/riscv: gdb: support vector registers for rv64 & rv32 > > LIU Zhiwei (3): > target/riscv: rvv-1.0: add mstatus VS field > target/riscv: rvv-1.0: add sstatus VS field > target/riscv: rvv-1.0: add vcsr register > > gdb-xml/riscv-32bit-csr.xml | 18 +- > gdb-xml/riscv-64bit-csr.xml | 18 +- > target/riscv/cpu.c | 11 +- > target/riscv/cpu.h | 95 +- > target/riscv/cpu_bits.h | 10 + > target/riscv/cpu_helper.c | 16 +- > target/riscv/csr.c | 79 +- > target/riscv/fpu_helper.c | 17 +- > target/riscv/gdbstub.c | 172 +- > target/riscv/helper.h | 495 ++-- > target/riscv/insn32-64.decode | 18 +- > target/riscv/insn32.decode | 288 +- > target/riscv/insn_trans/trans_rvv.c.inc | 2430 +++++++++++------ > target/riscv/internals.h | 22 +- > target/riscv/translate.c | 72 +- > target/riscv/vector_helper.c | 3316 +++++++++++------------ > 16 files changed, 4118 insertions(+), 2959 deletions(-) > > -- > 2.17.1 > > ping~ <div dir="ltr"><div dir="ltr">On Wed, Sep 30, 2020 at 3:04 AM <<a href="mailto:frank.chang@sifive.com">frank.chang@sifive.com</a>> wrote:<br></div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: Frank Chang <<a href="mailto:frank.chang@sifive.com" target="_blank">frank.chang@sifive.com</a>><br> <br> This patchset implements the vector extension v1.0 for RISC-V on QEMU.<br> <br> This patchset is sent as RFC because RVV v1.0 is still in draft state.<br> v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset.<br> <br> The port is available here:<br> <a href="https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v5" rel="noreferrer" target="_blank">https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v5</a><br> <br> You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0)<br> to run with RVV v1.0 instructions.<br> <br> Note: This patchset depends on two other patchsets listed in Based-on<br> section below so it might not able to be built unless those two<br> patchsets are applied.<br> <br> Changelog:<br> <br> v5<br> * refactor RVV v1.0 check functions.<br> (Thanks to Richard Henderson's bitwise tricks.)<br> * relax RV_VLEN_MAX to 1024-bits.<br> * implement vstart CSR's behaviors.<br> * trigger illegal instruction exception if frm is not valid for<br> vector floating-point instructions.<br> * rebase on riscv-to-apply.next.<br> <br> v4<br> * remove explicit float flmul variable in DisasContext.<br> * replace floating-point calculations with shift operations to<br> improve performance.<br> * relax RV_VLEN_MAX to 512-bits.<br> <br> v3<br> * apply nan-box helpers from Richard Henderson.<br> * remove fp16 api changes as they are sent independently in another<br> pathcset by Chih-Min Chao.<br> * remove all tail elements clear functions as tail elements can<br> retain unchanged for either VTA set to undisturbed or agnostic.<br> * add fp16 nan-box check generator function.<br> * add floating-point rounding mode enum.<br> * replace flmul arithmetic with shifts to avoid floating-point<br> conversions.<br> * add Zvqmac extension.<br> * replace gdbstub vector register xml files with dynamic generator.<br> * bumped to RVV v1.0.<br> * RVV v1.0 related changes:<br> * add vl<nf>re<eew>.v and vs<nf>r.v vector whole register<br> load/store instructions<br> * add vrgatherei16 instruction.<br> * rearranged bits in vtype to make vlmul bits into a contiguous<br> field.<br> <br> v2<br> * drop v0.7.1 support.<br> * replace invisible return check macros with functions.<br> * move mark_vs_dirty() to translators.<br> * add SSTATUS_VS flag for s-mode.<br> * nan-box scalar fp register for floating-point operations.<br> * add gdbstub files for vector registers to allow system-mode<br> debugging with GDB.<br> <br> Based-on: <<a href="http://20200909001647.532249-1-richard.henderson@linaro.org/" rel="noreferrer" target="_blank">20200909001647.532249-1-richard.henderson@linaro.org/</a>><br> Based-on: <<a href="http://1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/" rel="noreferrer" target="_blank">1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/</a>><br> <br> Frank Chang (62):<br> target/riscv: drop vector 0.7.1 and add 1.0 support<br> target/riscv: Use FIELD_EX32() to extract wd field<br> target/riscv: rvv-1.0: introduce writable misa.v field<br> target/riscv: rvv-1.0: add translation-time vector context status<br> target/riscv: rvv-1.0: remove rvv related codes from fcsr registers<br> target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr<br> registers<br> target/riscv: rvv-1.0: remove MLEN calculations<br> target/riscv: rvv-1.0: add fractional LMUL<br> target/riscv: rvv-1.0: add VMA and VTA<br> target/riscv: rvv-1.0: update check functions<br> target/riscv: introduce more imm value modes in translator functions<br> target/riscv: rvv:1.0: add translation-time nan-box helper function<br> target/riscv: rvv-1.0: configure instructions<br> target/riscv: rvv-1.0: stride load and store instructions<br> target/riscv: rvv-1.0: index load and store instructions<br> target/riscv: rvv-1.0: fix address index overflow bug of indexed<br> load/store insns<br> target/riscv: rvv-1.0: fault-only-first unit stride load<br> target/riscv: rvv-1.0: amo operations<br> target/riscv: rvv-1.0: load/store whole register instructions<br> target/riscv: rvv-1.0: update vext_max_elems() for load/store insns<br> target/riscv: rvv-1.0: take fractional LMUL into vector max elements<br> calculation<br> target/riscv: rvv-1.0: floating-point square-root instruction<br> target/riscv: rvv-1.0: floating-point classify instructions<br> target/riscv: rvv-1.0: mask population count instruction<br> target/riscv: rvv-1.0: find-first-set mask bit instruction<br> target/riscv: rvv-1.0: set-X-first mask bit instructions<br> target/riscv: rvv-1.0: iota instruction<br> target/riscv: rvv-1.0: element index instruction<br> target/riscv: rvv-1.0: allow load element with sign-extended<br> target/riscv: rvv-1.0: register gather instructions<br> target/riscv: rvv-1.0: integer scalar move instructions<br> target/riscv: rvv-1.0: floating-point move instruction<br> target/riscv: rvv-1.0: floating-point scalar move instructions<br> target/riscv: rvv-1.0: whole register move instructions<br> target/riscv: rvv-1.0: integer extension instructions<br> target/riscv: rvv-1.0: single-width averaging add and subtract<br> instructions<br> target/riscv: rvv-1.0: single-width bit shift instructions<br> target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow<br> target/riscv: rvv-1.0: narrowing integer right shift instructions<br> target/riscv: rvv-1.0: widening integer multiply-add instructions<br> target/riscv: rvv-1.0: single-width saturating add and subtract<br> instructions<br> target/riscv: rvv-1.0: integer comparison instructions<br> target/riscv: rvv-1.0: floating-point compare instructions<br> target/riscv: rvv-1.0: mask-register logical instructions<br> target/riscv: rvv-1.0: slide instructions<br> target/riscv: rvv-1.0: floating-point slide instructions<br> target/riscv: rvv-1.0: narrowing fixed-point clip instructions<br> target/riscv: rvv-1.0: single-width floating-point reduction<br> target/riscv: rvv-1.0: widening floating-point reduction instructions<br> target/riscv: rvv-1.0: single-width scaling shift instructions<br> target/riscv: rvv-1.0: remove widening saturating scaled multiply-add<br> target/riscv: rvv-1.0: remove vmford.vv and vmford.vf<br> target/riscv: rvv-1.0: remove integer extract instruction<br> target/riscv: rvv-1.0: floating-point min/max instructions<br> target/riscv: introduce floating-point rounding mode enum<br> target/riscv: rvv-1.0: floating-point/integer type-convert<br> instructions<br> target/riscv: rvv-1.0: widening floating-point/integer type-convert<br> target/riscv: add "set round to odd" rounding mode helper function<br> target/riscv: rvv-1.0: narrowing floating-point/integer type-convert<br> target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits<br> target/riscv: implement vstart CSR<br> target/riscv: trigger illegal instruction exception if frm is not<br> valid<br> <br> Greentime Hu (1):<br> target/riscv: rvv-1.0: add vlenb register<br> <br> Hsiangkai Wang (2):<br> target/riscv: gdb: modify gdb csr xml file to align with csr register<br> map<br> target/riscv: gdb: support vector registers for rv64 & rv32<br> <br> LIU Zhiwei (3):<br> target/riscv: rvv-1.0: add mstatus VS field<br> target/riscv: rvv-1.0: add sstatus VS field<br> target/riscv: rvv-1.0: add vcsr register<br> <br> gdb-xml/riscv-32bit-csr.xml | 18 +-<br> gdb-xml/riscv-64bit-csr.xml | 18 +-<br> target/riscv/cpu.c | 11 +-<br> target/riscv/cpu.h | 95 +-<br> target/riscv/cpu_bits.h | 10 +<br> target/riscv/cpu_helper.c | 16 +-<br> target/riscv/csr.c | 79 +-<br> target/riscv/fpu_helper.c | 17 +-<br> target/riscv/gdbstub.c | 172 +-<br> target/riscv/helper.h | 495 ++--<br> target/riscv/insn32-64.decode | 18 +-<br> target/riscv/insn32.decode | 288 +-<br> target/riscv/insn_trans/trans_rvv.c.inc | 2430 +++++++++++------<br> target/riscv/internals.h | 22 +-<br> target/riscv/translate.c | 72 +-<br> target/riscv/vector_helper.c | 3316 +++++++++++------------<br> 16 files changed, 4118 insertions(+), 2959 deletions(-)<br> <br> --<br> 2.17.1<br> <br></blockquote><div><br></div><div>ping~ </div></div></div>
ping 2nd~ On Tue, Oct 20, 2020 at 3:42 PM Frank Chang <frank.chang@sifive.com> wrote: > On Wed, Sep 30, 2020 at 3:04 AM <frank.chang@sifive.com> wrote: > >> From: Frank Chang <frank.chang@sifive.com> >> >> This patchset implements the vector extension v1.0 for RISC-V on QEMU. >> >> This patchset is sent as RFC because RVV v1.0 is still in draft state. >> v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 >> patchset. >> >> The port is available here: >> https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v5 >> >> You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0) >> to run with RVV v1.0 instructions. >> >> Note: This patchset depends on two other patchsets listed in Based-on >> section below so it might not able to be built unless those two >> patchsets are applied. >> >> Changelog: >> >> v5 >> * refactor RVV v1.0 check functions. >> (Thanks to Richard Henderson's bitwise tricks.) >> * relax RV_VLEN_MAX to 1024-bits. >> * implement vstart CSR's behaviors. >> * trigger illegal instruction exception if frm is not valid for >> vector floating-point instructions. >> * rebase on riscv-to-apply.next. >> >> v4 >> * remove explicit float flmul variable in DisasContext. >> * replace floating-point calculations with shift operations to >> improve performance. >> * relax RV_VLEN_MAX to 512-bits. >> >> v3 >> * apply nan-box helpers from Richard Henderson. >> * remove fp16 api changes as they are sent independently in another >> pathcset by Chih-Min Chao. >> * remove all tail elements clear functions as tail elements can >> retain unchanged for either VTA set to undisturbed or agnostic. >> * add fp16 nan-box check generator function. >> * add floating-point rounding mode enum. >> * replace flmul arithmetic with shifts to avoid floating-point >> conversions. >> * add Zvqmac extension. >> * replace gdbstub vector register xml files with dynamic generator. >> * bumped to RVV v1.0. >> * RVV v1.0 related changes: >> * add vl<nf>re<eew>.v and vs<nf>r.v vector whole register >> load/store instructions >> * add vrgatherei16 instruction. >> * rearranged bits in vtype to make vlmul bits into a contiguous >> field. >> >> v2 >> * drop v0.7.1 support. >> * replace invisible return check macros with functions. >> * move mark_vs_dirty() to translators. >> * add SSTATUS_VS flag for s-mode. >> * nan-box scalar fp register for floating-point operations. >> * add gdbstub files for vector registers to allow system-mode >> debugging with GDB. >> >> Based-on: <20200909001647.532249-1-richard.henderson@linaro.org/> >> Based-on: <1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/> >> >> Frank Chang (62): >> target/riscv: drop vector 0.7.1 and add 1.0 support >> target/riscv: Use FIELD_EX32() to extract wd field >> target/riscv: rvv-1.0: introduce writable misa.v field >> target/riscv: rvv-1.0: add translation-time vector context status >> target/riscv: rvv-1.0: remove rvv related codes from fcsr registers >> target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr >> registers >> target/riscv: rvv-1.0: remove MLEN calculations >> target/riscv: rvv-1.0: add fractional LMUL >> target/riscv: rvv-1.0: add VMA and VTA >> target/riscv: rvv-1.0: update check functions >> target/riscv: introduce more imm value modes in translator functions >> target/riscv: rvv:1.0: add translation-time nan-box helper function >> target/riscv: rvv-1.0: configure instructions >> target/riscv: rvv-1.0: stride load and store instructions >> target/riscv: rvv-1.0: index load and store instructions >> target/riscv: rvv-1.0: fix address index overflow bug of indexed >> load/store insns >> target/riscv: rvv-1.0: fault-only-first unit stride load >> target/riscv: rvv-1.0: amo operations >> target/riscv: rvv-1.0: load/store whole register instructions >> target/riscv: rvv-1.0: update vext_max_elems() for load/store insns >> target/riscv: rvv-1.0: take fractional LMUL into vector max elements >> calculation >> target/riscv: rvv-1.0: floating-point square-root instruction >> target/riscv: rvv-1.0: floating-point classify instructions >> target/riscv: rvv-1.0: mask population count instruction >> target/riscv: rvv-1.0: find-first-set mask bit instruction >> target/riscv: rvv-1.0: set-X-first mask bit instructions >> target/riscv: rvv-1.0: iota instruction >> target/riscv: rvv-1.0: element index instruction >> target/riscv: rvv-1.0: allow load element with sign-extended >> target/riscv: rvv-1.0: register gather instructions >> target/riscv: rvv-1.0: integer scalar move instructions >> target/riscv: rvv-1.0: floating-point move instruction >> target/riscv: rvv-1.0: floating-point scalar move instructions >> target/riscv: rvv-1.0: whole register move instructions >> target/riscv: rvv-1.0: integer extension instructions >> target/riscv: rvv-1.0: single-width averaging add and subtract >> instructions >> target/riscv: rvv-1.0: single-width bit shift instructions >> target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow >> target/riscv: rvv-1.0: narrowing integer right shift instructions >> target/riscv: rvv-1.0: widening integer multiply-add instructions >> target/riscv: rvv-1.0: single-width saturating add and subtract >> instructions >> target/riscv: rvv-1.0: integer comparison instructions >> target/riscv: rvv-1.0: floating-point compare instructions >> target/riscv: rvv-1.0: mask-register logical instructions >> target/riscv: rvv-1.0: slide instructions >> target/riscv: rvv-1.0: floating-point slide instructions >> target/riscv: rvv-1.0: narrowing fixed-point clip instructions >> target/riscv: rvv-1.0: single-width floating-point reduction >> target/riscv: rvv-1.0: widening floating-point reduction instructions >> target/riscv: rvv-1.0: single-width scaling shift instructions >> target/riscv: rvv-1.0: remove widening saturating scaled multiply-add >> target/riscv: rvv-1.0: remove vmford.vv and vmford.vf >> target/riscv: rvv-1.0: remove integer extract instruction >> target/riscv: rvv-1.0: floating-point min/max instructions >> target/riscv: introduce floating-point rounding mode enum >> target/riscv: rvv-1.0: floating-point/integer type-convert >> instructions >> target/riscv: rvv-1.0: widening floating-point/integer type-convert >> target/riscv: add "set round to odd" rounding mode helper function >> target/riscv: rvv-1.0: narrowing floating-point/integer type-convert >> target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits >> target/riscv: implement vstart CSR >> target/riscv: trigger illegal instruction exception if frm is not >> valid >> >> Greentime Hu (1): >> target/riscv: rvv-1.0: add vlenb register >> >> Hsiangkai Wang (2): >> target/riscv: gdb: modify gdb csr xml file to align with csr register >> map >> target/riscv: gdb: support vector registers for rv64 & rv32 >> >> LIU Zhiwei (3): >> target/riscv: rvv-1.0: add mstatus VS field >> target/riscv: rvv-1.0: add sstatus VS field >> target/riscv: rvv-1.0: add vcsr register >> >> gdb-xml/riscv-32bit-csr.xml | 18 +- >> gdb-xml/riscv-64bit-csr.xml | 18 +- >> target/riscv/cpu.c | 11 +- >> target/riscv/cpu.h | 95 +- >> target/riscv/cpu_bits.h | 10 + >> target/riscv/cpu_helper.c | 16 +- >> target/riscv/csr.c | 79 +- >> target/riscv/fpu_helper.c | 17 +- >> target/riscv/gdbstub.c | 172 +- >> target/riscv/helper.h | 495 ++-- >> target/riscv/insn32-64.decode | 18 +- >> target/riscv/insn32.decode | 288 +- >> target/riscv/insn_trans/trans_rvv.c.inc | 2430 +++++++++++------ >> target/riscv/internals.h | 22 +- >> target/riscv/translate.c | 72 +- >> target/riscv/vector_helper.c | 3316 +++++++++++------------ >> 16 files changed, 4118 insertions(+), 2959 deletions(-) >> >> -- >> 2.17.1 >> >> > ping~ > <div dir="ltr">ping 2nd~</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Oct 20, 2020 at 3:42 PM Frank Chang <<a href="mailto:frank.chang@sifive.com">frank.chang@sifive.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><div dir="ltr">On Wed, Sep 30, 2020 at 3:04 AM <<a href="mailto:frank.chang@sifive.com" target="_blank">frank.chang@sifive.com</a>> wrote:<br></div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: Frank Chang <<a href="mailto:frank.chang@sifive.com" target="_blank">frank.chang@sifive.com</a>><br> <br> This patchset implements the vector extension v1.0 for RISC-V on QEMU.<br> <br> This patchset is sent as RFC because RVV v1.0 is still in draft state.<br> v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset.<br> <br> The port is available here:<br> <a href="https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v5" rel="noreferrer" target="_blank">https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v5</a><br> <br> You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0)<br> to run with RVV v1.0 instructions.<br> <br> Note: This patchset depends on two other patchsets listed in Based-on<br> section below so it might not able to be built unless those two<br> patchsets are applied.<br> <br> Changelog:<br> <br> v5<br> * refactor RVV v1.0 check functions.<br> (Thanks to Richard Henderson's bitwise tricks.)<br> * relax RV_VLEN_MAX to 1024-bits.<br> * implement vstart CSR's behaviors.<br> * trigger illegal instruction exception if frm is not valid for<br> vector floating-point instructions.<br> * rebase on riscv-to-apply.next.<br> <br> v4<br> * remove explicit float flmul variable in DisasContext.<br> * replace floating-point calculations with shift operations to<br> improve performance.<br> * relax RV_VLEN_MAX to 512-bits.<br> <br> v3<br> * apply nan-box helpers from Richard Henderson.<br> * remove fp16 api changes as they are sent independently in another<br> pathcset by Chih-Min Chao.<br> * remove all tail elements clear functions as tail elements can<br> retain unchanged for either VTA set to undisturbed or agnostic.<br> * add fp16 nan-box check generator function.<br> * add floating-point rounding mode enum.<br> * replace flmul arithmetic with shifts to avoid floating-point<br> conversions.<br> * add Zvqmac extension.<br> * replace gdbstub vector register xml files with dynamic generator.<br> * bumped to RVV v1.0.<br> * RVV v1.0 related changes:<br> * add vl<nf>re<eew>.v and vs<nf>r.v vector whole register<br> load/store instructions<br> * add vrgatherei16 instruction.<br> * rearranged bits in vtype to make vlmul bits into a contiguous<br> field.<br> <br> v2<br> * drop v0.7.1 support.<br> * replace invisible return check macros with functions.<br> * move mark_vs_dirty() to translators.<br> * add SSTATUS_VS flag for s-mode.<br> * nan-box scalar fp register for floating-point operations.<br> * add gdbstub files for vector registers to allow system-mode<br> debugging with GDB.<br> <br> Based-on: <<a href="http://20200909001647.532249-1-richard.henderson@linaro.org/" rel="noreferrer" target="_blank">20200909001647.532249-1-richard.henderson@linaro.org/</a>><br> Based-on: <<a href="http://1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/" rel="noreferrer" target="_blank">1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/</a>><br> <br> Frank Chang (62):<br> target/riscv: drop vector 0.7.1 and add 1.0 support<br> target/riscv: Use FIELD_EX32() to extract wd field<br> target/riscv: rvv-1.0: introduce writable misa.v field<br> target/riscv: rvv-1.0: add translation-time vector context status<br> target/riscv: rvv-1.0: remove rvv related codes from fcsr registers<br> target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr<br> registers<br> target/riscv: rvv-1.0: remove MLEN calculations<br> target/riscv: rvv-1.0: add fractional LMUL<br> target/riscv: rvv-1.0: add VMA and VTA<br> target/riscv: rvv-1.0: update check functions<br> target/riscv: introduce more imm value modes in translator functions<br> target/riscv: rvv:1.0: add translation-time nan-box helper function<br> target/riscv: rvv-1.0: configure instructions<br> target/riscv: rvv-1.0: stride load and store instructions<br> target/riscv: rvv-1.0: index load and store instructions<br> target/riscv: rvv-1.0: fix address index overflow bug of indexed<br> load/store insns<br> target/riscv: rvv-1.0: fault-only-first unit stride load<br> target/riscv: rvv-1.0: amo operations<br> target/riscv: rvv-1.0: load/store whole register instructions<br> target/riscv: rvv-1.0: update vext_max_elems() for load/store insns<br> target/riscv: rvv-1.0: take fractional LMUL into vector max elements<br> calculation<br> target/riscv: rvv-1.0: floating-point square-root instruction<br> target/riscv: rvv-1.0: floating-point classify instructions<br> target/riscv: rvv-1.0: mask population count instruction<br> target/riscv: rvv-1.0: find-first-set mask bit instruction<br> target/riscv: rvv-1.0: set-X-first mask bit instructions<br> target/riscv: rvv-1.0: iota instruction<br> target/riscv: rvv-1.0: element index instruction<br> target/riscv: rvv-1.0: allow load element with sign-extended<br> target/riscv: rvv-1.0: register gather instructions<br> target/riscv: rvv-1.0: integer scalar move instructions<br> target/riscv: rvv-1.0: floating-point move instruction<br> target/riscv: rvv-1.0: floating-point scalar move instructions<br> target/riscv: rvv-1.0: whole register move instructions<br> target/riscv: rvv-1.0: integer extension instructions<br> target/riscv: rvv-1.0: single-width averaging add and subtract<br> instructions<br> target/riscv: rvv-1.0: single-width bit shift instructions<br> target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow<br> target/riscv: rvv-1.0: narrowing integer right shift instructions<br> target/riscv: rvv-1.0: widening integer multiply-add instructions<br> target/riscv: rvv-1.0: single-width saturating add and subtract<br> instructions<br> target/riscv: rvv-1.0: integer comparison instructions<br> target/riscv: rvv-1.0: floating-point compare instructions<br> target/riscv: rvv-1.0: mask-register logical instructions<br> target/riscv: rvv-1.0: slide instructions<br> target/riscv: rvv-1.0: floating-point slide instructions<br> target/riscv: rvv-1.0: narrowing fixed-point clip instructions<br> target/riscv: rvv-1.0: single-width floating-point reduction<br> target/riscv: rvv-1.0: widening floating-point reduction instructions<br> target/riscv: rvv-1.0: single-width scaling shift instructions<br> target/riscv: rvv-1.0: remove widening saturating scaled multiply-add<br> target/riscv: rvv-1.0: remove vmford.vv and vmford.vf<br> target/riscv: rvv-1.0: remove integer extract instruction<br> target/riscv: rvv-1.0: floating-point min/max instructions<br> target/riscv: introduce floating-point rounding mode enum<br> target/riscv: rvv-1.0: floating-point/integer type-convert<br> instructions<br> target/riscv: rvv-1.0: widening floating-point/integer type-convert<br> target/riscv: add "set round to odd" rounding mode helper function<br> target/riscv: rvv-1.0: narrowing floating-point/integer type-convert<br> target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits<br> target/riscv: implement vstart CSR<br> target/riscv: trigger illegal instruction exception if frm is not<br> valid<br> <br> Greentime Hu (1):<br> target/riscv: rvv-1.0: add vlenb register<br> <br> Hsiangkai Wang (2):<br> target/riscv: gdb: modify gdb csr xml file to align with csr register<br> map<br> target/riscv: gdb: support vector registers for rv64 & rv32<br> <br> LIU Zhiwei (3):<br> target/riscv: rvv-1.0: add mstatus VS field<br> target/riscv: rvv-1.0: add sstatus VS field<br> target/riscv: rvv-1.0: add vcsr register<br> <br> gdb-xml/riscv-32bit-csr.xml | 18 +-<br> gdb-xml/riscv-64bit-csr.xml | 18 +-<br> target/riscv/cpu.c | 11 +-<br> target/riscv/cpu.h | 95 +-<br> target/riscv/cpu_bits.h | 10 +<br> target/riscv/cpu_helper.c | 16 +-<br> target/riscv/csr.c | 79 +-<br> target/riscv/fpu_helper.c | 17 +-<br> target/riscv/gdbstub.c | 172 +-<br> target/riscv/helper.h | 495 ++--<br> target/riscv/insn32-64.decode | 18 +-<br> target/riscv/insn32.decode | 288 +-<br> target/riscv/insn_trans/trans_rvv.c.inc | 2430 +++++++++++------<br> target/riscv/internals.h | 22 +-<br> target/riscv/translate.c | 72 +-<br> target/riscv/vector_helper.c | 3316 +++++++++++------------<br> 16 files changed, 4118 insertions(+), 2959 deletions(-)<br> <br> --<br> 2.17.1<br> <br></blockquote><div><br></div><div>ping~ </div></div></div> </blockquote></div>
On Mon, Nov 9, 2020 at 6:09 PM Frank Chang <frank.chang@sifive.com> wrote: > > ping 2nd~ I mentioned earlier that I will wait until this becomes a patch series to review it. Overall it looks like it's on the right track though. Alistair > > On Tue, Oct 20, 2020 at 3:42 PM Frank Chang <frank.chang@sifive.com> wrote: >> >> On Wed, Sep 30, 2020 at 3:04 AM <frank.chang@sifive.com> wrote: >>> >>> From: Frank Chang <frank.chang@sifive.com> >>> >>> This patchset implements the vector extension v1.0 for RISC-V on QEMU. >>> >>> This patchset is sent as RFC because RVV v1.0 is still in draft state. >>> v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset. >>> >>> The port is available here: >>> https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v5 >>> >>> You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0) >>> to run with RVV v1.0 instructions. >>> >>> Note: This patchset depends on two other patchsets listed in Based-on >>> section below so it might not able to be built unless those two >>> patchsets are applied. >>> >>> Changelog: >>> >>> v5 >>> * refactor RVV v1.0 check functions. >>> (Thanks to Richard Henderson's bitwise tricks.) >>> * relax RV_VLEN_MAX to 1024-bits. >>> * implement vstart CSR's behaviors. >>> * trigger illegal instruction exception if frm is not valid for >>> vector floating-point instructions. >>> * rebase on riscv-to-apply.next. >>> >>> v4 >>> * remove explicit float flmul variable in DisasContext. >>> * replace floating-point calculations with shift operations to >>> improve performance. >>> * relax RV_VLEN_MAX to 512-bits. >>> >>> v3 >>> * apply nan-box helpers from Richard Henderson. >>> * remove fp16 api changes as they are sent independently in another >>> pathcset by Chih-Min Chao. >>> * remove all tail elements clear functions as tail elements can >>> retain unchanged for either VTA set to undisturbed or agnostic. >>> * add fp16 nan-box check generator function. >>> * add floating-point rounding mode enum. >>> * replace flmul arithmetic with shifts to avoid floating-point >>> conversions. >>> * add Zvqmac extension. >>> * replace gdbstub vector register xml files with dynamic generator. >>> * bumped to RVV v1.0. >>> * RVV v1.0 related changes: >>> * add vl<nf>re<eew>.v and vs<nf>r.v vector whole register >>> load/store instructions >>> * add vrgatherei16 instruction. >>> * rearranged bits in vtype to make vlmul bits into a contiguous >>> field. >>> >>> v2 >>> * drop v0.7.1 support. >>> * replace invisible return check macros with functions. >>> * move mark_vs_dirty() to translators. >>> * add SSTATUS_VS flag for s-mode. >>> * nan-box scalar fp register for floating-point operations. >>> * add gdbstub files for vector registers to allow system-mode >>> debugging with GDB. >>> >>> Based-on: <20200909001647.532249-1-richard.henderson@linaro.org/> >>> Based-on: <1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/> >>> >>> Frank Chang (62): >>> target/riscv: drop vector 0.7.1 and add 1.0 support >>> target/riscv: Use FIELD_EX32() to extract wd field >>> target/riscv: rvv-1.0: introduce writable misa.v field >>> target/riscv: rvv-1.0: add translation-time vector context status >>> target/riscv: rvv-1.0: remove rvv related codes from fcsr registers >>> target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr >>> registers >>> target/riscv: rvv-1.0: remove MLEN calculations >>> target/riscv: rvv-1.0: add fractional LMUL >>> target/riscv: rvv-1.0: add VMA and VTA >>> target/riscv: rvv-1.0: update check functions >>> target/riscv: introduce more imm value modes in translator functions >>> target/riscv: rvv:1.0: add translation-time nan-box helper function >>> target/riscv: rvv-1.0: configure instructions >>> target/riscv: rvv-1.0: stride load and store instructions >>> target/riscv: rvv-1.0: index load and store instructions >>> target/riscv: rvv-1.0: fix address index overflow bug of indexed >>> load/store insns >>> target/riscv: rvv-1.0: fault-only-first unit stride load >>> target/riscv: rvv-1.0: amo operations >>> target/riscv: rvv-1.0: load/store whole register instructions >>> target/riscv: rvv-1.0: update vext_max_elems() for load/store insns >>> target/riscv: rvv-1.0: take fractional LMUL into vector max elements >>> calculation >>> target/riscv: rvv-1.0: floating-point square-root instruction >>> target/riscv: rvv-1.0: floating-point classify instructions >>> target/riscv: rvv-1.0: mask population count instruction >>> target/riscv: rvv-1.0: find-first-set mask bit instruction >>> target/riscv: rvv-1.0: set-X-first mask bit instructions >>> target/riscv: rvv-1.0: iota instruction >>> target/riscv: rvv-1.0: element index instruction >>> target/riscv: rvv-1.0: allow load element with sign-extended >>> target/riscv: rvv-1.0: register gather instructions >>> target/riscv: rvv-1.0: integer scalar move instructions >>> target/riscv: rvv-1.0: floating-point move instruction >>> target/riscv: rvv-1.0: floating-point scalar move instructions >>> target/riscv: rvv-1.0: whole register move instructions >>> target/riscv: rvv-1.0: integer extension instructions >>> target/riscv: rvv-1.0: single-width averaging add and subtract >>> instructions >>> target/riscv: rvv-1.0: single-width bit shift instructions >>> target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow >>> target/riscv: rvv-1.0: narrowing integer right shift instructions >>> target/riscv: rvv-1.0: widening integer multiply-add instructions >>> target/riscv: rvv-1.0: single-width saturating add and subtract >>> instructions >>> target/riscv: rvv-1.0: integer comparison instructions >>> target/riscv: rvv-1.0: floating-point compare instructions >>> target/riscv: rvv-1.0: mask-register logical instructions >>> target/riscv: rvv-1.0: slide instructions >>> target/riscv: rvv-1.0: floating-point slide instructions >>> target/riscv: rvv-1.0: narrowing fixed-point clip instructions >>> target/riscv: rvv-1.0: single-width floating-point reduction >>> target/riscv: rvv-1.0: widening floating-point reduction instructions >>> target/riscv: rvv-1.0: single-width scaling shift instructions >>> target/riscv: rvv-1.0: remove widening saturating scaled multiply-add >>> target/riscv: rvv-1.0: remove vmford.vv and vmford.vf >>> target/riscv: rvv-1.0: remove integer extract instruction >>> target/riscv: rvv-1.0: floating-point min/max instructions >>> target/riscv: introduce floating-point rounding mode enum >>> target/riscv: rvv-1.0: floating-point/integer type-convert >>> instructions >>> target/riscv: rvv-1.0: widening floating-point/integer type-convert >>> target/riscv: add "set round to odd" rounding mode helper function >>> target/riscv: rvv-1.0: narrowing floating-point/integer type-convert >>> target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits >>> target/riscv: implement vstart CSR >>> target/riscv: trigger illegal instruction exception if frm is not >>> valid >>> >>> Greentime Hu (1): >>> target/riscv: rvv-1.0: add vlenb register >>> >>> Hsiangkai Wang (2): >>> target/riscv: gdb: modify gdb csr xml file to align with csr register >>> map >>> target/riscv: gdb: support vector registers for rv64 & rv32 >>> >>> LIU Zhiwei (3): >>> target/riscv: rvv-1.0: add mstatus VS field >>> target/riscv: rvv-1.0: add sstatus VS field >>> target/riscv: rvv-1.0: add vcsr register >>> >>> gdb-xml/riscv-32bit-csr.xml | 18 +- >>> gdb-xml/riscv-64bit-csr.xml | 18 +- >>> target/riscv/cpu.c | 11 +- >>> target/riscv/cpu.h | 95 +- >>> target/riscv/cpu_bits.h | 10 + >>> target/riscv/cpu_helper.c | 16 +- >>> target/riscv/csr.c | 79 +- >>> target/riscv/fpu_helper.c | 17 +- >>> target/riscv/gdbstub.c | 172 +- >>> target/riscv/helper.h | 495 ++-- >>> target/riscv/insn32-64.decode | 18 +- >>> target/riscv/insn32.decode | 288 +- >>> target/riscv/insn_trans/trans_rvv.c.inc | 2430 +++++++++++------ >>> target/riscv/internals.h | 22 +- >>> target/riscv/translate.c | 72 +- >>> target/riscv/vector_helper.c | 3316 +++++++++++------------ >>> 16 files changed, 4118 insertions(+), 2959 deletions(-) >>> >>> -- >>> 2.17.1 >>> >> >> ping~
From: Frank Chang <frank.chang@sifive.com> This patchset implements the vector extension v1.0 for RISC-V on QEMU. This patchset is sent as RFC because RVV v1.0 is still in draft state. v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset. The port is available here: https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v5 You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0) to run with RVV v1.0 instructions. Note: This patchset depends on two other patchsets listed in Based-on section below so it might not able to be built unless those two patchsets are applied. Changelog: v5 * refactor RVV v1.0 check functions. (Thanks to Richard Henderson's bitwise tricks.) * relax RV_VLEN_MAX to 1024-bits. * implement vstart CSR's behaviors. * trigger illegal instruction exception if frm is not valid for vector floating-point instructions. * rebase on riscv-to-apply.next. v4 * remove explicit float flmul variable in DisasContext. * replace floating-point calculations with shift operations to improve performance. * relax RV_VLEN_MAX to 512-bits. v3 * apply nan-box helpers from Richard Henderson. * remove fp16 api changes as they are sent independently in another pathcset by Chih-Min Chao. * remove all tail elements clear functions as tail elements can retain unchanged for either VTA set to undisturbed or agnostic. * add fp16 nan-box check generator function. * add floating-point rounding mode enum. * replace flmul arithmetic with shifts to avoid floating-point conversions. * add Zvqmac extension. * replace gdbstub vector register xml files with dynamic generator. * bumped to RVV v1.0. * RVV v1.0 related changes: * add vl<nf>re<eew>.v and vs<nf>r.v vector whole register load/store instructions * add vrgatherei16 instruction. * rearranged bits in vtype to make vlmul bits into a contiguous field. v2 * drop v0.7.1 support. * replace invisible return check macros with functions. * move mark_vs_dirty() to translators. * add SSTATUS_VS flag for s-mode. * nan-box scalar fp register for floating-point operations. * add gdbstub files for vector registers to allow system-mode debugging with GDB. Based-on: <20200909001647.532249-1-richard.henderson@linaro.org/> Based-on: <1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/> Frank Chang (62): target/riscv: drop vector 0.7.1 and add 1.0 support target/riscv: Use FIELD_EX32() to extract wd field target/riscv: rvv-1.0: introduce writable misa.v field target/riscv: rvv-1.0: add translation-time vector context status target/riscv: rvv-1.0: remove rvv related codes from fcsr registers target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers target/riscv: rvv-1.0: remove MLEN calculations target/riscv: rvv-1.0: add fractional LMUL target/riscv: rvv-1.0: add VMA and VTA target/riscv: rvv-1.0: update check functions target/riscv: introduce more imm value modes in translator functions target/riscv: rvv:1.0: add translation-time nan-box helper function target/riscv: rvv-1.0: configure instructions target/riscv: rvv-1.0: stride load and store instructions target/riscv: rvv-1.0: index load and store instructions target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns target/riscv: rvv-1.0: fault-only-first unit stride load target/riscv: rvv-1.0: amo operations target/riscv: rvv-1.0: load/store whole register instructions target/riscv: rvv-1.0: update vext_max_elems() for load/store insns target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation target/riscv: rvv-1.0: floating-point square-root instruction target/riscv: rvv-1.0: floating-point classify instructions target/riscv: rvv-1.0: mask population count instruction target/riscv: rvv-1.0: find-first-set mask bit instruction target/riscv: rvv-1.0: set-X-first mask bit instructions target/riscv: rvv-1.0: iota instruction target/riscv: rvv-1.0: element index instruction target/riscv: rvv-1.0: allow load element with sign-extended target/riscv: rvv-1.0: register gather instructions target/riscv: rvv-1.0: integer scalar move instructions target/riscv: rvv-1.0: floating-point move instruction target/riscv: rvv-1.0: floating-point scalar move instructions target/riscv: rvv-1.0: whole register move instructions target/riscv: rvv-1.0: integer extension instructions target/riscv: rvv-1.0: single-width averaging add and subtract instructions target/riscv: rvv-1.0: single-width bit shift instructions target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow target/riscv: rvv-1.0: narrowing integer right shift instructions target/riscv: rvv-1.0: widening integer multiply-add instructions target/riscv: rvv-1.0: single-width saturating add and subtract instructions target/riscv: rvv-1.0: integer comparison instructions target/riscv: rvv-1.0: floating-point compare instructions target/riscv: rvv-1.0: mask-register logical instructions target/riscv: rvv-1.0: slide instructions target/riscv: rvv-1.0: floating-point slide instructions target/riscv: rvv-1.0: narrowing fixed-point clip instructions target/riscv: rvv-1.0: single-width floating-point reduction target/riscv: rvv-1.0: widening floating-point reduction instructions target/riscv: rvv-1.0: single-width scaling shift instructions target/riscv: rvv-1.0: remove widening saturating scaled multiply-add target/riscv: rvv-1.0: remove vmford.vv and vmford.vf target/riscv: rvv-1.0: remove integer extract instruction target/riscv: rvv-1.0: floating-point min/max instructions target/riscv: introduce floating-point rounding mode enum target/riscv: rvv-1.0: floating-point/integer type-convert instructions target/riscv: rvv-1.0: widening floating-point/integer type-convert target/riscv: add "set round to odd" rounding mode helper function target/riscv: rvv-1.0: narrowing floating-point/integer type-convert target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits target/riscv: implement vstart CSR target/riscv: trigger illegal instruction exception if frm is not valid Greentime Hu (1): target/riscv: rvv-1.0: add vlenb register Hsiangkai Wang (2): target/riscv: gdb: modify gdb csr xml file to align with csr register map target/riscv: gdb: support vector registers for rv64 & rv32 LIU Zhiwei (3): target/riscv: rvv-1.0: add mstatus VS field target/riscv: rvv-1.0: add sstatus VS field target/riscv: rvv-1.0: add vcsr register gdb-xml/riscv-32bit-csr.xml | 18 +- gdb-xml/riscv-64bit-csr.xml | 18 +- target/riscv/cpu.c | 11 +- target/riscv/cpu.h | 95 +- target/riscv/cpu_bits.h | 10 + target/riscv/cpu_helper.c | 16 +- target/riscv/csr.c | 79 +- target/riscv/fpu_helper.c | 17 +- target/riscv/gdbstub.c | 172 +- target/riscv/helper.h | 495 ++-- target/riscv/insn32-64.decode | 18 +- target/riscv/insn32.decode | 288 +- target/riscv/insn_trans/trans_rvv.c.inc | 2430 +++++++++++------ target/riscv/internals.h | 22 +- target/riscv/translate.c | 72 +- target/riscv/vector_helper.c | 3316 +++++++++++------------ 16 files changed, 4118 insertions(+), 2959 deletions(-) -- 2.17.1