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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At Edgar's request, generating the pull-request for this. r~ The following changes since commit 39335fab59e11cfda9b7cf63929825db2dd3a3e0: Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request' into staging (2020-08-28 22:30:11 +0100) are available in the Git repository at: https://github.com/rth7680/qemu.git tags/pull-mb-20200831 for you to fetch changes up to 7233c0d0b0f5b65fcf6d6423de069ddf9f916392: target/microblaze: Reduce linux-user address space to 32-bit (2020-08-31 08:45:45 -0700) ---------------------------------------------------------------- Convert microblaze to generic translator loop Convert microblaze to decodetree Fix mb_cpu_transaction_failed Other misc cleanups ---------------------------------------------------------------- Richard Henderson (76): tests/tcg: Add microblaze to arches filter tests/tcg: Do not require FE_TOWARDZERO tests/tcg: Do not require FE_* exception bits target/microblaze: Tidy gdbstub target/microblaze: Split out PC from env->sregs target/microblaze: Split out MSR from env->sregs target/microblaze: Split out EAR from env->sregs target/microblaze: Split out ESR from env->sregs target/microblaze: Split out FSR from env->sregs target/microblaze: Split out BTR from env->sregs target/microblaze: Split out EDR from env->sregs target/microblaze: Split the cpu_SR array target/microblaze: Fix width of PC and BTARGET target/microblaze: Fix width of MSR target/microblaze: Fix width of ESR target/microblaze: Fix width of FSR target/microblaze: Fix width of BTR target/microblaze: Fix width of EDR target/microblaze: Remove cpu_ear target/microblaze: Tidy raising of exceptions target/microblaze: Mark raise_exception as noreturn target/microblaze: Remove helper_debug and env->debug target/microblaze: Rename env_* tcg variables to cpu_* target/microblaze: Tidy mb_tcg_init target/microblaze: Split out MSR[C] to its own variable target/microblaze: Use DISAS_NORETURN target/microblaze: Check singlestep_enabled in gen_goto_tb target/microblaze: Convert to DisasContextBase target/microblaze: Convert to translator_loop target/microblaze: Remove SIM_COMPAT target/microblaze: Remove DISAS_GNU target/microblaze: Remove empty D macros target/microblaze: Remove LOG_DIS target/microblaze: Ensure imm constant is always available target/microblaze: Add decodetree infrastructure target/microblaze: Convert dec_add to decodetree target/microblaze: Convert dec_sub to decodetree target/microblaze: Implement cmp and cmpu inline target/microblaze: Convert dec_pattern to decodetree target/microblaze: Convert dec_and, dec_or, dec_xor to decodetree target/microblaze: Convert dec_mul to decodetree target/microblaze: Convert dec_div to decodetree target/microblaze: Unwind properly when raising divide-by-zero target/microblaze: Convert dec_bit to decodetree target/microblaze: Convert dec_barrel to decodetree target/microblaze: Convert dec_imm to decodetree target/microblaze: Convert dec_fpu to decodetree target/microblaze: Fix cpu unwind for fpu exceptions target/microblaze: Mark fpu helpers TCG_CALL_NO_WG target/microblaze: Replace MSR_EE_FLAG with MSR_EE target/microblaze: Cache mem_index in DisasContext target/microblaze: Fix cpu unwind for stackprot target/microblaze: Convert dec_load and dec_store to decodetree target/microblaze: Assert no overlap in flags making up tb_flags target/microblaze: Move bimm to BIMM_FLAG target/microblaze: Fix no-op mb_cpu_transaction_failed target/microblaze: Store "current" iflags in insn_start tcg: Add tcg_get_insn_start_param target/microblaze: Use cc->do_unaligned_access target/microblaze: Replace clear_imm with tb_flags_to_set target/microblaze: Replace delayed_branch with tb_flags_to_set target/microblaze: Tidy mb_cpu_dump_state target/microblaze: Convert brk and brki to decodetree target/microblaze: Convert mbar to decodetree target/microblaze: Reorganize branching target/microblaze: Convert dec_br to decodetree target/microblaze: Convert dec_bcc to decodetree target/microblaze: Convert dec_rts to decodetree target/microblaze: Tidy do_rti, do_rtb, do_rte target/microblaze: Convert msrclr, msrset to decodetree target/microblaze: Convert dec_msr to decodetree target/microblaze: Convert dec_stream to decodetree target/microblaze: Remove last of old decoder target/microblaze: Remove cpu_R[0] target/microblaze: Add flags markup to some helpers target/microblaze: Reduce linux-user address space to 32-bit include/tcg/tcg.h | 15 + target/microblaze/cpu-param.h | 15 + target/microblaze/cpu.h | 67 +- target/microblaze/helper.h | 49 +- target/microblaze/microblaze-decode.h | 59 - tests/tcg/multiarch/float_helpers.h | 17 + target/microblaze/insns.decode | 256 +++ linux-user/elfload.c | 9 +- linux-user/microblaze/cpu_loop.c | 26 +- linux-user/microblaze/signal.c | 8 +- target/microblaze/cpu.c | 9 +- target/microblaze/gdbstub.c | 193 +- target/microblaze/helper.c | 164 +- target/microblaze/mmu.c | 4 +- target/microblaze/op_helper.c | 194 +- target/microblaze/translate.c | 3223 +++++++++++++++++---------------- tests/tcg/multiarch/float_convs.c | 2 + tests/tcg/multiarch/float_madds.c | 2 + target/microblaze/meson.build | 3 + tests/tcg/configure.sh | 2 +- 20 files changed, 2292 insertions(+), 2025 deletions(-) delete mode 100644 target/microblaze/microblaze-decode.h create mode 100644 target/microblaze/insns.decode