mbox series

[PULL,00/15] riscv-to-apply queue

Message ID 20200603161352.744204-1-alistair.francis@wdc.com
Headers show
Series riscv-to-apply queue | expand

Message

Alistair Francis June 3, 2020, 4:13 p.m. UTC 
The following changes since commit 5cc7a54c2e91d82cb6a52e4921325c511fd90712:

  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200602' into staging (2020-06-02 18:16:38 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200603

for you to fetch changes up to fe0fe4735e798578097758781166cc221319b93d:

  riscv: Initial commit of OpenTitan machine (2020-06-03 09:11:51 -0700)

----------------------------------------------------------------
This is a collection of RISC-V patches for 5.1.

This incldues removing deprecated features and part of the OpenTitan
support series.

----------------------------------------------------------------
Alistair Francis (11):
      hw/riscv: spike: Remove deprecated ISA specific machines
      target/riscv: Remove the deprecated CPUs
      target/riscv: Drop support for ISA spec version 1.09.1
      docs: deprecated: Update the -bios documentation
      riscv: sifive_e: Manually define the machine
      riscv/boot: Add a missing header include
      target/riscv: Don't overwrite the reset vector
      target/riscv: Disable the MMU correctly
      target/riscv: Don't set PMP feature in the cpu init
      target/riscv: Add the lowRISC Ibex CPU
      riscv: Initial commit of OpenTitan machine

Bin Meng (4):
      riscv: Suppress the error report for QEMU testing with riscv_find_firmware()
      riscv: Change the default behavior if no -bios option is specified
      hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
      hw/riscv: virt: Remove the riscv_ prefix of the machine* functions

 docs/system/deprecated.rst                     |  98 +++++------
 default-configs/riscv32-softmmu.mak            |   1 +
 default-configs/riscv64-softmmu.mak            |  11 +-
 include/hw/riscv/boot.h                        |   1 +
 include/hw/riscv/opentitan.h                   |  68 ++++++++
 include/hw/riscv/sifive_e.h                    |   4 +
 include/hw/riscv/spike.h                       |   6 +-
 target/riscv/cpu.h                             |   9 +-
 hw/riscv/boot.c                                |  45 ++---
 hw/riscv/opentitan.c                           | 184 +++++++++++++++++++++
 hw/riscv/sifive_e.c                            |  41 +++--
 hw/riscv/sifive_u.c                            |  24 +--
 hw/riscv/spike.c                               | 217 -------------------------
 hw/riscv/virt.c                                |  20 +--
 target/riscv/cpu.c                             |  45 ++---
 target/riscv/cpu_helper.c                      |  82 ++++------
 target/riscv/csr.c                             | 138 +++-------------
 target/riscv/insn_trans/trans_privileged.inc.c |  18 +-
 target/riscv/monitor.c                         |   5 -
 target/riscv/op_helper.c                       |  17 +-
 tests/qtest/machine-none-test.c                |   4 +-
 MAINTAINERS                                    |   9 +
 hw/riscv/Kconfig                               |   5 +
 hw/riscv/Makefile.objs                         |   1 +
 24 files changed, 480 insertions(+), 573 deletions(-)
 create mode 100644 include/hw/riscv/opentitan.h
 create mode 100644 hw/riscv/opentitan.c