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d="scan'208";a="137935126" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2020 02:37:04 +0800 IronPort-SDR: 62ykwJIudIHRRjtow64sxiI8BA0AYD2N91pP12yWlaeIzbeUlFTXe4noKO0Qw9SshMrpNcK0U3 4pdSBbrpBFjnFu21KbDsjpgGYWGmHXlXo= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 11:27:08 -0700 IronPort-SDR: t3qSngCryoWVlFS84BFNntMO/IxERhDyrcbbdq/91Z0rqEFe5vKzzDqZqZIFvGKnjqusWGXeoc vRnfN8Fvvx1A== WDCIronportException: Internal Received: from cnf007834.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.55.253]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2020 11:37:02 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 00/14] RISC-V Patch Queue for 5.1 Date: Wed, 29 Apr 2020 11:28:42 -0700 Message-Id: <20200429182856.2588202-1-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 14:37:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , palmerdabbelt@google.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit a7922a3c81f34f45b1ebc9670a7769edc4c42a43: Open 5.1 development tree (2020-04-29 15:07:10 +0100) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200429-1 for you to fetch changes up to 23766b6a35d5b1664ab782c02624bf2435c4ed5d: hw/riscv/spike: Allow more than one CPUs (2020-04-29 11:23:44 -0700) ---------------------------------------------------------------- RISC-V pull request for 5.1 This is the first pull request for the 5.1 development period. It contains all of the patches that were sent during the 5.0 timeframe. This is an assortment of fixes for RISC-V, including fixes for the Hypervisor extension, the Spike machine and an update to OpenSBI. ---------------------------------------------------------------- Alistair Francis (4): riscv/sifive_u: Fix up file ordering riscv/sifive_u: Add a serial property to the sifive_u SoC riscv: Don't use stage-2 PTE lookup protection flags riscv: AND stage-1 and stage-2 protection flags Anup Patel (4): riscv: Fix Stage2 SV32 page table walk hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() hw/riscv/spike: Allow loading firmware separately using -bios option hw/riscv/spike: Allow more than one CPUs Bin Meng (3): riscv/sifive_u: Add a serial property to the sifive_u machine hw/riscv: Generate correct "mmu-type" for 32-bit machines roms: opensbi: Upgrade from v0.6 to v0.7 Corey Wharton (2): riscv: sifive_e: Support changing CPU type target/riscv: Add a sifive-e34 cpu type LIU Zhiwei (1): linux-user/riscv: fix up struct target_ucontext definition hw/riscv/boot.c | 13 ++- hw/riscv/sifive_e.c | 5 +- hw/riscv/sifive_u.c | 143 ++++++++++++++++----------- hw/riscv/spike.c | 30 +++++- hw/riscv/virt.c | 6 +- include/hw/riscv/boot.h | 6 +- include/hw/riscv/sifive_u.h | 3 + linux-user/riscv/signal.c | 3 +- pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin | Bin 49472 -> 49520 bytes pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 41280 -> 49504 bytes pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 53760 -> 57936 bytes pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 49664 -> 57920 bytes roms/opensbi | 2 +- target/riscv/cpu.c | 10 ++ target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 18 ++-- 16 files changed, 160 insertions(+), 80 deletions(-)