From patchwork Thu Mar 26 23:08:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184938 Delivered-To: patch@linaro.org Received: by 2002:a92:de47:0:0:0:0:0 with SMTP id e7csp636826ilr; Thu, 26 Mar 2020 16:08:59 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtbs5yN7LFexL6bOmmJdBAZoVyBvwO0rBvFppm8osXtcymLD8eHxO4paPJWg60gV1Ro4/s/ X-Received: by 2002:a05:6214:12c7:: with SMTP id s7mr11365335qvv.218.1585264139204; Thu, 26 Mar 2020 16:08:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1585264139; cv=none; d=google.com; s=arc-20160816; b=T0EEhe6ZhncPMIUpgN9es5BFYTry3DF4TPkPx/bT9zDN+d2C8c5aVz9+l438g9hFPo 1qp2PY/gQlxGjCovxGf9/Pqjb+gzBntk/6ra1p3qjJSSt54E20O+WP7yPaBJ71AJK9fC Jz1UCsC7imKe6PPz4+n9HuF82rdaFRao7dBf8+SPeIeZP0uL1YRLuLGNGwoxuXsa5Y0L bhgED+zMCD8lUbqWnuSuVhHDFVBxMagY2ISmavCGR6JObkPs6rbkzHS0ugTcwaF8Xa4O 927sJAX4C6yW454I45Ka7SQRxYS4lxqyLfF3+6+YD1NBVl5onSw68pRBB0zLtZ8IpuVW SdXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:to:from:dkim-signature; bh=F6i9arXen4TLeK0sY1KC/vE3U9xI96E0JovDA1nAh+A=; b=I7ugATxGEqd1ZEzxkEW2n9558mQdj6Y1XX/11ZFfJZJLzJ0/598WM6prcfI2Vh/Ne7 hIcVViZQWnwV7RZZWiiCBwejKCfuK2qBc/vLjCf5GCL7F3Ia5KULKJF0u+LG+qltGvI/ 77v06YyIMMxq6BWOqa7avtWDObTcrJ4hyYoX+VaOFOn80opAinP9gVazG+z8kxnNDkC2 QZJPFyR9ULUHF++e+Lp071+MCp3ZFOPQYQBxNiTbgQ24WNDVSsGG1q0pjg3Mqz3R+9Jc PqSzyjD8IJlFIzU3md7Uqb+PCRAfKO9Tomo0fvpmouOwXxljMT9/2qNUSbg1Q0vS96HS Yu8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ax2U9u49; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b128si2428347qke.202.2020.03.26.16.08.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Mar 2020 16:08:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ax2U9u49; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jHbcQ-0001qZ-Gw for patch@linaro.org; Thu, 26 Mar 2020 19:08:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57769) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jHbcB-0001q7-SD for qemu-devel@nongnu.org; Thu, 26 Mar 2020 19:08:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jHbcA-0001EF-5b for qemu-devel@nongnu.org; Thu, 26 Mar 2020 19:08:43 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:36313) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jHbcA-0001E2-0j for qemu-devel@nongnu.org; Thu, 26 Mar 2020 19:08:42 -0400 Received: by mail-pl1-x62c.google.com with SMTP id g2so2741988plo.3 for ; Thu, 26 Mar 2020 16:08:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=F6i9arXen4TLeK0sY1KC/vE3U9xI96E0JovDA1nAh+A=; b=ax2U9u49VmY0gE13qfwVJclO+B1Tzk6x0lBTKlYeB8FjPOuL4aesEUgEYCiT+/iWbu Ti66yszpdyU6RBxsu7tM92nCKns3X/0HhuRzBHFsm5PsXwfOARJ8FZIMrD6KvD92HTsw OaSQJiTBxacF5By+QvK9OlhAD0WfayjBqQwMGCmyggrVQ/1Esp1fZ/TxmOftAG10Aevs lPpDbDXLHqRtcgxNg7qiKff0toKJLRIQyJQACRgEppCDIRL6kvRfr/3xpcaJudFHaEQC duXYrQuJot/hgEvrKeKxV1MJ8TpZBdoyzZqZHySpriR5yQGpYDkAO/T6MQO48ASnmnfg 7XNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=F6i9arXen4TLeK0sY1KC/vE3U9xI96E0JovDA1nAh+A=; b=cEG9tuCizI3xwttgcHxxWpqmS98vYqCbMarv1Hn/aednbFvWky+tebx7tXuz4+GKNc 6aslJ+Wzm6lzSz1McAHUX2pQCsy4PE05IufmDiwm9i3VhP+hWShi29RujovgAaKgfTVJ FaQIo8hmRIr0ZotLPeZuBsW1Vw5JwH4LUvRHZ9NfKjueuUA2kmObfQKlE0x+d+OACF6Y bXmN0xO5eaVJxhmm/Pd+c7CkUdluODoRlo8BpC5yJyQK7+hKYKB/yGMZhaNi5k9Cqczm Wl2pcjyS274aXDP4tzHaU+T/Bd7529S3GVq9NwCHSWlTkHNb81sZTMxFS6OJerd/t44K tucQ== X-Gm-Message-State: ANhLgQ0MiLi3Fy3/M4VCEHN1afYC5RYbxP9HI1uCRXiaMtNESMOO/Z/q ANkBfOuzjcAgsUnFHBHgHAvHD8NUc7c= X-Received: by 2002:a17:90a:208:: with SMTP id c8mr2561202pjc.153.1585264120482; Thu, 26 Mar 2020 16:08:40 -0700 (PDT) Received: from localhost.localdomain (174-21-138-234.tukw.qwest.net. [174.21.138.234]) by smtp.gmail.com with ESMTPSA id i187sm2530037pfg.33.2020.03.26.16.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2020 16:08:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-5.1 00/31] target/arm: SVE2, part 1 Date: Thu, 26 Mar 2020 16:08:07 -0700 Message-Id: <20200326230838.31112-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: rajav@quicinc.com, qemu-arm@nongnu.org, apazos@quicinc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Posting this for early review. It's based on some other patch sets that I have posted recently that also touch SVE, listed below. But it might just be easier to clone the devel tree [2]. While the branch itself will rebase frequently for development, I've also created a tag, post-sve2-20200326, for this posting. This is mostly untested, as the most recently released Foundation Model does not support SVE2. Some of the new instructions overlap with old fashioned NEON, and I can verify that those have not broken, and show that SVE2 will use the same code path. But the predicated insns and bottom/top interleaved insns are not yet RISU testable, as I have nothing to compare against. The patches are in general arranged so that one complete group of insns are added at once. The groups within the manual [1] have so far been small-ish. r~ --- [1] ISA manual: https://static.docs.arm.com/ddi0602/d/ISA_A64_xml_futureA-2019-12_OPT.pdf [2] Devel tree: https://github.com/rth7680/qemu/tree/tgt-arm-sve-2 Based-on: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=163610 ("target/arm: sve load/store improvements") Based-on: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=164500 ("target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA") Based-on: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=164048 ("target/arm: Implement ARMv8.5-MemTag, system mode") Richard Henderson (31): target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 target/arm: Implement SVE2 Integer Multiply - Unpredicated target/arm: Implement SVE2 integer pairwise add and accumulate long target/arm: Remove fp_status from helper_{recpe,rsqrte}_u32 target/arm: Implement SVE2 integer unary operations (predicated) target/arm: Split out saturating/rounding shifts from neon target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) target/arm: Implement SVE2 integer halving add/subtract (predicated) target/arm: Implement SVE2 integer pairwise arithmetic target/arm: Implement SVE2 saturating add/subtract (predicated) target/arm: Implement SVE2 integer add/subtract long target/arm: Implement SVE2 integer add/subtract interleaved long target/arm: Implement SVE2 integer add/subtract wide target/arm: Implement SVE2 integer multiply long target/arm: Implement PMULLB and PMULLT target/arm: Tidy SVE tszimm shift formats target/arm: Implement SVE2 bitwise shift left long target/arm: Implement SVE2 bitwise exclusive-or interleaved target/arm: Implement SVE2 bitwise permute target/arm: Implement SVE2 complex integer add target/arm: Implement SVE2 integer absolute difference and accumulate long target/arm: Implement SVE2 integer add/subtract long with carry target/arm: Create arm_gen_gvec_[us]sra target/arm: Create arm_gen_gvec_{u,s}{rshr,rsra} target/arm: Implement SVE2 bitwise shift right and accumulate target/arm: Create arm_gen_gvec_{sri,sli} target/arm: Tidy handle_vec_simd_shri target/arm: Implement SVE2 bitwise shift and insert target/arm: Vectorize SABD/UABD target/arm: Vectorize SABA/UABA target/arm: Implement SVE2 integer absolute difference and accumulate target/arm/cpu.h | 31 ++ target/arm/helper-sve.h | 345 +++++++++++++++++ target/arm/helper.h | 81 +++- target/arm/translate-a64.h | 9 + target/arm/translate.h | 24 +- target/arm/vec_internal.h | 161 ++++++++ target/arm/sve.decode | 217 ++++++++++- target/arm/helper.c | 3 +- target/arm/kvm64.c | 2 + target/arm/neon_helper.c | 515 ++++--------------------- target/arm/sve_helper.c | 757 ++++++++++++++++++++++++++++++++++--- target/arm/translate-a64.c | 557 +++++++++++++++++++++++---- target/arm/translate-sve.c | 557 +++++++++++++++++++++++++++ target/arm/translate.c | 626 ++++++++++++++++++++++-------- target/arm/vec_helper.c | 411 ++++++++++++++++++++ target/arm/vfp_helper.c | 4 +- 16 files changed, 3532 insertions(+), 768 deletions(-) create mode 100644 target/arm/vec_internal.h -- 2.20.1