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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id g69sm6824842pje.34.2020.03.12.12.42.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 12:42:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 00/42] target/arm: Implement ARMv8.5-MemTag, system mode Date: Thu, 12 Mar 2020 12:41:37 -0700 Message-Id: <20200312194219.24406-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" I've done quite a lot of reorg since v5, so much so that I've dropped most of the review tags that had been given. There are a couple of major improvements to note: * The effective ATA bit is in hflags, noting whether access to the allocation tags is enabled by the OS. This is moderately expensive to compute, so it's better to hold on to that. This allows trivial inlining of some of the operations. * Updates for SVE, and thus Based-on: <20200311064420.30606-1-richard.henderson@linaro.org> ("target/arm: sve load/store improvements") * Architecture updates, to F.a released this month. * There are now real patches for the kernel: git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git devel/mte-v2 Booting that and running my user-mode tests showed up a few bugs. r~ Richard Henderson (42): target/arm: Add isar tests for mte target/arm: Improve masking of SCR RES0 bits target/arm: Add support for MTE to SCTLR_ELx target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT target/arm: Add DISAS_UPDATE_NOCHAIN target/arm: Add MTE system registers target/arm: Add MTE bits to tb_flags target/arm: Implement the IRG instruction target/arm: Implement the ADDG, SUBG instructions target/arm: Implement the GMI instruction target/arm: Implement the SUBP instruction target/arm: Define arm_cpu_do_unaligned_access for user-only target/arm: Add helper_probe_access target/arm: Implement LDG, STG, ST2G instructions target/arm: Implement the STGP instruction target/arm: Restrict the values of DCZID.BS under TCG target/arm: Simplify DC_ZVA target/arm: Implement the LDGM, STGM, STZGM instructions target/arm: Implement the access tag cache flushes target/arm: Move regime_el to internals.h target/arm: Move regime_tcr to internals.h target/arm: Add gen_mte_check1 target/arm: Add gen_mte_checkN target/arm: Implement helper_mte_check1 target/arm: Implement helper_mte_checkN target/arm: Add helper_mte_check_zva target/arm: Use mte_checkN for sve unpredicated loads target/arm: Use mte_checkN for sve unpredicated stores target/arm: Use mte_check1 for sve LD1R target/arm: Add mte helpers for sve scalar + int loads target/arm: Add mte helpers for sve scalar + int stores target/arm: Add mte helpers for sve scalar + int ff/nf loads target/arm: Handle TBI for sve scalar + int memory ops target/arm: Add mte helpers for sve scatter/gather memory ops target/arm: Complete TBI clearing for user-only for SVE target/arm: Implement data cache set allocation tags target/arm: Set PSTATE.TCO on exception entry target/arm: Enable MTE target/arm: Cache the Tagged bit for a page in MemTxAttrs target/arm: Create tagged ram when MTE is enabled target/arm: Add allocation tag storage for system mode target/arm/cpu.h | 36 +- target/arm/helper-a64.h | 16 + target/arm/helper-sve.h | 491 +++++++++++ target/arm/helper.h | 2 + target/arm/internals.h | 145 ++++ target/arm/translate-a64.h | 5 + target/arm/translate.h | 23 +- hw/arm/virt.c | 52 ++ linux-user/aarch64/cpu_loop.c | 7 + linux-user/arm/cpu_loop.c | 7 + target/arm/cpu.c | 79 +- target/arm/cpu64.c | 1 + target/arm/helper-a64.c | 94 +-- target/arm/helper.c | 350 ++++++-- target/arm/mte_helper.c | 894 ++++++++++++++++++++ target/arm/op_helper.c | 16 + target/arm/sve_helper.c | 750 ++++++++++++++--- target/arm/tlb_helper.c | 41 +- target/arm/translate-a64.c | 607 ++++++++++++-- target/arm/translate-sve.c | 1425 ++++++++++++++++++++------------ target/arm/translate-vfp.inc.c | 2 +- target/arm/translate.c | 16 +- target/arm/Makefile.objs | 1 + 23 files changed, 4204 insertions(+), 856 deletions(-) create mode 100644 target/arm/mte_helper.c -- 2.20.1