| Message ID | 20190510185438.29533-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | tcg: Add CPUClass::tlb_fill | expand |
On May 10, 2019 8:55 PM, "Richard Henderson" <richard.henderson@linaro.org> wrote: > > Changes in v2: > > * Fix --disable-tcg compilation for x86 and s390x. > I adjusted every target/ that used any CONFIG_TCG in cpu.c. > but then afterward I see that only x86 and s390x have had > their Makefiles adjusted to make --disable-tcg actually work. > > * Fix Werror for 64-bit on 32-bit. > > Only re-posting changed patches. > Hello, Richard. Just want to stress that there are unaddressed concerns for patch 12/27. Thanks, Aleksamdar > > r~ > > > The following changes since commit efb4f3b62c69383a7308d7b739a3193e7c0ccae8: > > Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2019-05-10 14:49:36 +0100) > > are available in the Git repository at: > > https://github.com/rth7680/qemu.git tags/pull-tcg-20190510 > > for you to fetch changes up to 4811e9095c0491bc6f5450e5012c9c4796b9e59d: > > tcg: Use tlb_fill probe from tlb_vaddr_to_host (2019-05-10 11:12:50 -0700) > > ---------------------------------------------------------------- > Add CPUClass::tlb_fill. > Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. > > ---------------------------------------------------------------- > Richard Henderson (27): > tcg: Add CPUClass::tlb_fill > target/alpha: Convert to CPUClass::tlb_fill > target/arm: Convert to CPUClass::tlb_fill > target/cris: Convert to CPUClass::tlb_fill > target/hppa: Convert to CPUClass::tlb_fill > target/i386: Convert to CPUClass::tlb_fill > target/lm32: Convert to CPUClass::tlb_fill > target/m68k: Convert to CPUClass::tlb_fill > target/microblaze: Convert to CPUClass::tlb_fill > target/mips: Pass a valid error to raise_mmu_exception for user-only > target/mips: Tidy control flow in mips_cpu_handle_mmu_fault > target/mips: Convert to CPUClass::tlb_fill > target/moxie: Convert to CPUClass::tlb_fill > target/nios2: Convert to CPUClass::tlb_fill > target/openrisc: Convert to CPUClass::tlb_fill > target/ppc: Convert to CPUClass::tlb_fill > target/riscv: Convert to CPUClass::tlb_fill > target/s390x: Convert to CPUClass::tlb_fill > target/sh4: Convert to CPUClass::tlb_fill > target/sparc: Convert to CPUClass::tlb_fill > target/tilegx: Convert to CPUClass::tlb_fill > target/tricore: Convert to CPUClass::tlb_fill > target/unicore32: Convert to CPUClass::tlb_fill > target/xtensa: Convert to CPUClass::tlb_fill > tcg: Use CPUClass::tlb_fill in cputlb.c > tcg: Remove CPUClass::handle_mmu_fault > tcg: Use tlb_fill probe from tlb_vaddr_to_host > > include/exec/cpu_ldst.h | 50 +++-------- > include/exec/exec-all.h | 9 -- > include/qom/cpu.h | 12 ++- > target/alpha/cpu.h | 5 +- > target/arm/internals.h | 10 ++- > target/cris/cpu.h | 5 +- > target/hppa/cpu.h | 8 +- > target/i386/cpu.h | 5 +- > target/lm32/cpu.h | 5 +- > target/m68k/cpu.h | 5 +- > target/microblaze/cpu.h | 5 +- > target/mips/internal.h | 5 +- > target/moxie/cpu.h | 5 +- > target/nios2/cpu.h | 5 +- > target/openrisc/cpu.h | 5 +- > target/ppc/cpu.h | 7 +- > target/riscv/cpu.h | 5 +- > target/s390x/internal.h | 5 +- > target/sh4/cpu.h | 5 +- > target/sparc/cpu.h | 5 +- > target/tricore/cpu.h | 6 +- > target/unicore32/cpu.h | 5 +- > target/xtensa/cpu.h | 5 +- > accel/tcg/cputlb.c | 88 +++++++++++++++++-- > accel/tcg/user-exec.c | 36 ++------ > target/alpha/cpu.c | 5 +- > target/alpha/helper.c | 24 +++-- > target/alpha/mem_helper.c | 16 ---- > target/arm/cpu.c | 22 +---- > target/arm/helper.c | 90 +++++++++++-------- > target/arm/op_helper.c | 29 +----- > target/arm/sve_helper.c | 6 +- > target/cris/cpu.c | 5 +- > target/cris/helper.c | 61 ++++++------- > target/cris/op_helper.c | 28 ------ > target/hppa/cpu.c | 5 +- > target/hppa/mem_helper.c | 16 ++-- > target/i386/cpu.c | 5 +- > target/i386/excp_helper.c | 53 ++++++----- > target/i386/mem_helper.c | 21 ----- > target/lm32/cpu.c | 5 +- > target/lm32/helper.c | 8 +- > target/lm32/op_helper.c | 16 ---- > target/m68k/cpu.c | 2 +- > target/m68k/helper.c | 89 +++++++++---------- > target/m68k/op_helper.c | 15 ---- > target/microblaze/cpu.c | 5 +- > target/microblaze/helper.c | 101 ++++++++++----------- > target/microblaze/op_helper.c | 19 ---- > target/mips/cpu.c | 5 +- > target/mips/helper.c | 81 ++++++++--------- > target/mips/op_helper.c | 15 ---- > target/moxie/cpu.c | 5 +- > target/moxie/helper.c | 65 +++----------- > target/nios2/cpu.c | 5 +- > target/nios2/helper.c | 170 +++++++++++++++++------------------- > target/nios2/mmu.c | 12 --- > target/openrisc/cpu.c | 5 +- > target/openrisc/mmu.c | 69 +++++++-------- > target/ppc/mmu_helper.c | 16 ++-- > target/ppc/translate_init.inc.c | 5 +- > target/ppc/user_only_helper.c | 14 +-- > target/riscv/cpu.c | 5 +- > target/riscv/cpu_helper.c | 50 +++++------ > target/s390x/cpu.c | 5 +- > target/s390x/excp_helper.c | 67 +++++++++----- > target/s390x/mem_helper.c | 16 ---- > target/sh4/cpu.c | 5 +- > target/sh4/helper.c | 189 +++++++++++++++++++--------------------- > target/sh4/op_helper.c | 12 --- > target/sparc/cpu.c | 5 +- > target/sparc/ldst_helper.c | 15 ---- > target/sparc/mmu_helper.c | 58 +++++++----- > target/tilegx/cpu.c | 10 ++- > target/tricore/cpu.c | 1 + > target/tricore/helper.c | 23 +++-- > target/tricore/op_helper.c | 26 ------ > target/unicore32/cpu.c | 5 +- > target/unicore32/helper.c | 23 ----- > target/unicore32/op_helper.c | 14 --- > target/unicore32/softmmu.c | 13 ++- > target/xtensa/cpu.c | 5 +- > target/xtensa/helper.c | 33 ++++--- > 83 files changed, 868 insertions(+), 1131 deletions(-) >
On Fri, 10 May 2019 at 19:54, Richard Henderson <richard.henderson@linaro.org> wrote: > > Changes in v2: > > * Fix --disable-tcg compilation for x86 and s390x. > I adjusted every target/ that used any CONFIG_TCG in cpu.c. > but then afterward I see that only x86 and s390x have had > their Makefiles adjusted to make --disable-tcg actually work. > > * Fix Werror for 64-bit on 32-bit. > > Only re-posting changed patches. > > > r~ > > > The following changes since commit efb4f3b62c69383a7308d7b739a3193e7c0ccae8: > > Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2019-05-10 14:49:36 +0100) > > are available in the Git repository at: > > https://github.com/rth7680/qemu.git tags/pull-tcg-20190510 > > for you to fetch changes up to 4811e9095c0491bc6f5450e5012c9c4796b9e59d: > > tcg: Use tlb_fill probe from tlb_vaddr_to_host (2019-05-10 11:12:50 -0700) > > ---------------------------------------------------------------- > Add CPUClass::tlb_fill. > Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. > I did a test merge of this and it passed my build tests; I haven't applied it though pending resolution of Aleksandar's comments. thanks -- PMM
On Tue, 14 May 2019 at 13:36, Peter Maydell <peter.maydell@linaro.org> wrote: > > On Fri, 10 May 2019 at 19:54, Richard Henderson > <richard.henderson@linaro.org> wrote: > > > > Changes in v2: > > > > * Fix --disable-tcg compilation for x86 and s390x. > > I adjusted every target/ that used any CONFIG_TCG in cpu.c. > > but then afterward I see that only x86 and s390x have had > > their Makefiles adjusted to make --disable-tcg actually work. > > > > * Fix Werror for 64-bit on 32-bit. > > > > Only re-posting changed patches. > > > > > > r~ > > > > > > The following changes since commit efb4f3b62c69383a7308d7b739a3193e7c0ccae8: > > > > Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2019-05-10 14:49:36 +0100) > > > > are available in the Git repository at: > > > > https://github.com/rth7680/qemu.git tags/pull-tcg-20190510 > > > > for you to fetch changes up to 4811e9095c0491bc6f5450e5012c9c4796b9e59d: > > > > tcg: Use tlb_fill probe from tlb_vaddr_to_host (2019-05-10 11:12:50 -0700) > > > > ---------------------------------------------------------------- > > Add CPUClass::tlb_fill. > > Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. > > > > I did a test merge of this and it passed my build tests; I haven't > applied it though pending resolution of Aleksandar's comments. Applied, thanks (conclusion of mailing list discussion was that it was ok to apply as-is). Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1 for any user-visible changes. -- PMM
Changes in v2: * Fix --disable-tcg compilation for x86 and s390x. I adjusted every target/ that used any CONFIG_TCG in cpu.c. but then afterward I see that only x86 and s390x have had their Makefiles adjusted to make --disable-tcg actually work. * Fix Werror for 64-bit on 32-bit. Only re-posting changed patches. r~ The following changes since commit efb4f3b62c69383a7308d7b739a3193e7c0ccae8: Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2019-05-10 14:49:36 +0100) are available in the Git repository at: https://github.com/rth7680/qemu.git tags/pull-tcg-20190510 for you to fetch changes up to 4811e9095c0491bc6f5450e5012c9c4796b9e59d: tcg: Use tlb_fill probe from tlb_vaddr_to_host (2019-05-10 11:12:50 -0700) ---------------------------------------------------------------- Add CPUClass::tlb_fill. Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. ---------------------------------------------------------------- Richard Henderson (27): tcg: Add CPUClass::tlb_fill target/alpha: Convert to CPUClass::tlb_fill target/arm: Convert to CPUClass::tlb_fill target/cris: Convert to CPUClass::tlb_fill target/hppa: Convert to CPUClass::tlb_fill target/i386: Convert to CPUClass::tlb_fill target/lm32: Convert to CPUClass::tlb_fill target/m68k: Convert to CPUClass::tlb_fill target/microblaze: Convert to CPUClass::tlb_fill target/mips: Pass a valid error to raise_mmu_exception for user-only target/mips: Tidy control flow in mips_cpu_handle_mmu_fault target/mips: Convert to CPUClass::tlb_fill target/moxie: Convert to CPUClass::tlb_fill target/nios2: Convert to CPUClass::tlb_fill target/openrisc: Convert to CPUClass::tlb_fill target/ppc: Convert to CPUClass::tlb_fill target/riscv: Convert to CPUClass::tlb_fill target/s390x: Convert to CPUClass::tlb_fill target/sh4: Convert to CPUClass::tlb_fill target/sparc: Convert to CPUClass::tlb_fill target/tilegx: Convert to CPUClass::tlb_fill target/tricore: Convert to CPUClass::tlb_fill target/unicore32: Convert to CPUClass::tlb_fill target/xtensa: Convert to CPUClass::tlb_fill tcg: Use CPUClass::tlb_fill in cputlb.c tcg: Remove CPUClass::handle_mmu_fault tcg: Use tlb_fill probe from tlb_vaddr_to_host include/exec/cpu_ldst.h | 50 +++-------- include/exec/exec-all.h | 9 -- include/qom/cpu.h | 12 ++- target/alpha/cpu.h | 5 +- target/arm/internals.h | 10 ++- target/cris/cpu.h | 5 +- target/hppa/cpu.h | 8 +- target/i386/cpu.h | 5 +- target/lm32/cpu.h | 5 +- target/m68k/cpu.h | 5 +- target/microblaze/cpu.h | 5 +- target/mips/internal.h | 5 +- target/moxie/cpu.h | 5 +- target/nios2/cpu.h | 5 +- target/openrisc/cpu.h | 5 +- target/ppc/cpu.h | 7 +- target/riscv/cpu.h | 5 +- target/s390x/internal.h | 5 +- target/sh4/cpu.h | 5 +- target/sparc/cpu.h | 5 +- target/tricore/cpu.h | 6 +- target/unicore32/cpu.h | 5 +- target/xtensa/cpu.h | 5 +- accel/tcg/cputlb.c | 88 +++++++++++++++++-- accel/tcg/user-exec.c | 36 ++------ target/alpha/cpu.c | 5 +- target/alpha/helper.c | 24 +++-- target/alpha/mem_helper.c | 16 ---- target/arm/cpu.c | 22 +---- target/arm/helper.c | 90 +++++++++++-------- target/arm/op_helper.c | 29 +----- target/arm/sve_helper.c | 6 +- target/cris/cpu.c | 5 +- target/cris/helper.c | 61 ++++++------- target/cris/op_helper.c | 28 ------ target/hppa/cpu.c | 5 +- target/hppa/mem_helper.c | 16 ++-- target/i386/cpu.c | 5 +- target/i386/excp_helper.c | 53 ++++++----- target/i386/mem_helper.c | 21 ----- target/lm32/cpu.c | 5 +- target/lm32/helper.c | 8 +- target/lm32/op_helper.c | 16 ---- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 89 +++++++++---------- target/m68k/op_helper.c | 15 ---- target/microblaze/cpu.c | 5 +- target/microblaze/helper.c | 101 ++++++++++----------- target/microblaze/op_helper.c | 19 ---- target/mips/cpu.c | 5 +- target/mips/helper.c | 81 ++++++++--------- target/mips/op_helper.c | 15 ---- target/moxie/cpu.c | 5 +- target/moxie/helper.c | 65 +++----------- target/nios2/cpu.c | 5 +- target/nios2/helper.c | 170 +++++++++++++++++------------------- target/nios2/mmu.c | 12 --- target/openrisc/cpu.c | 5 +- target/openrisc/mmu.c | 69 +++++++-------- target/ppc/mmu_helper.c | 16 ++-- target/ppc/translate_init.inc.c | 5 +- target/ppc/user_only_helper.c | 14 +-- target/riscv/cpu.c | 5 +- target/riscv/cpu_helper.c | 50 +++++------ target/s390x/cpu.c | 5 +- target/s390x/excp_helper.c | 67 +++++++++----- target/s390x/mem_helper.c | 16 ---- target/sh4/cpu.c | 5 +- target/sh4/helper.c | 189 +++++++++++++++++++--------------------- target/sh4/op_helper.c | 12 --- target/sparc/cpu.c | 5 +- target/sparc/ldst_helper.c | 15 ---- target/sparc/mmu_helper.c | 58 +++++++----- target/tilegx/cpu.c | 10 ++- target/tricore/cpu.c | 1 + target/tricore/helper.c | 23 +++-- target/tricore/op_helper.c | 26 ------ target/unicore32/cpu.c | 5 +- target/unicore32/helper.c | 23 ----- target/unicore32/op_helper.c | 14 --- target/unicore32/softmmu.c | 13 ++- target/xtensa/cpu.c | 5 +- target/xtensa/helper.c | 33 ++++--- 83 files changed, 868 insertions(+), 1131 deletions(-)