From patchwork Fri Dec 7 10:36:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153108 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp335126ljp; Fri, 7 Dec 2018 02:37:11 -0800 (PST) X-Google-Smtp-Source: AFSGD/VVLYgpWgBAIunrw4BJnrGHMkWdUJ7afkpDspHfffScl42u3tw448KJVlO9NKzbYG+l1H5X X-Received: by 2002:a0c:cb85:: with SMTP id p5mr1385395qvk.162.1544179031479; Fri, 07 Dec 2018 02:37:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179031; cv=none; d=google.com; s=arc-20160816; b=ppbaJWKjBkQUqtwSaxDUJ9HI7Ug8bEhz1zTpcboVZ1zurpxhxyNK6tIO9oBBNo/RPw CnuILGG2n/OMbEuRgTOwpLj7em+Ho0iutuRSNBqGaE5C6wJrP5aSNvgoiUoNuIy3uUXk jBbSWrUmhKk36aGfnHx/mVDrfIPNJePMktMBO+ucIm6ZCbD+MuvJIHC+YjimU/nJ+oXi q7hGS/EttPoVtn721clcf9iT3N7hhyf1dVisjjsHZs8hF9CWswu4TOw/RBwCjym9+Kob 68nur58WdmUzuzq5lEkYex2RY1urQOBbkjuTHOCA5N6PQ8IZntSXh5uInRa6eXcsKjR/ eX+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:message-id:date:to:from :dkim-signature; bh=WMBd9oa7MC0i1KQh0tNBD8NRs+lYrHiXU4mCCcwHzq8=; b=cA5T5trj/2PZTvBFkkqbp1P70zSE98Fzcr7KGEeg+nYmaXGxxMmg9GwxG9bVPpeWZf JZZVwEy5gma/jdzdNwCsTkPcwHgiBoPA+2ie44HczWigi7G9xTur8x4pzigKv1VlLWFG qQqANCOHJfN+cVjzNNKzi3jRH8lT4f8kIIaTXhCy49KCgkBJvFSPnFefm4E8rKlWG9Ml XJ75AeH8VU6k7FmJMqr8G16ueZWpzAd9emdhHYaUdo+Z33GfJuYhlHL6faxjmjoPYQeN uUVfdkqEfHZL2Td2T/M6Bc4nNtpolM37xGCm1yITTSH+UWUqvI3lKmQWWKL2Iv12q0dz NVvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Z+1pgmcA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s16si1812150qtq.248.2018.12.07.02.37.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:37:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Z+1pgmcA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVO-0007y3-R4 for patch@linaro.org; Fri, 07 Dec 2018 05:37:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDUv-0007xo-Qm for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDUs-0007BN-If for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:41 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:37100) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDUs-0007AZ-4c for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:36:38 -0500 Received: by mail-oi1-x244.google.com with SMTP id y23so3000315oia.4 for ; Fri, 07 Dec 2018 02:36:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=WMBd9oa7MC0i1KQh0tNBD8NRs+lYrHiXU4mCCcwHzq8=; b=Z+1pgmcALSyWNK20UX+JGO/kPyb4vMRWzFje5I8DQmESeBVHuodM/7jN2hcZXqhBfG MC2TgbrbXAZX2LIyeEUdqnJ//YrYVbvpopGyPEZp3IvOIf0z/dxXK0wIGGFk+z16JFod Ip20RLiIJwP0pmta/tsvT7GPoK4FpTDtLqsM0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WMBd9oa7MC0i1KQh0tNBD8NRs+lYrHiXU4mCCcwHzq8=; b=oqcOFDmCWCyVTKV+uAsgFmbQ3mfjahwkQMnnzwkx5uQ2Vrl3+5ceDHDdsceaB2fHvs 4IAzmj5XzWQ+kCEqwd4bPNdA9rRUSkou2nY5QVOV0b5Cm7rKuNze9SiTMnIxtXVOVMB4 KrP1Xkz0xCF6YBbUif1Uxp1sZc9eELERsCTY7FI3zOGewFAqIXtwxq/jZlrSdUxTHO1M 5VW89xucZHz0+9upM5NmPo27vCADa8cLwcinzNbeNZa4FXd8u5iFVe8sJ/Zln+uVKA/q L6SXsy+QxefIL5M2cJXolquYD/dzupRNmCAn7wSS5nDPHsqUAnZs5KY+HRC9XZnb7zk8 DwFw== X-Gm-Message-State: AA+aEWbTw5f3aRi55Bs/VQI4qiaWDDA46rMOVvkhOv5EuTixAMyUQa5n jZkDUCzJ7fthGHk7pgmlakMVtwQ1eAE= X-Received: by 2002:aca:6841:: with SMTP id d62mr945783oic.351.1544178996387; Fri, 07 Dec 2018 02:36:36 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:36:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:05 -0600 Message-Id: <20181207103631.28193-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH 00/26] target/arm: Implement ARMv8.3-PAuth X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This has survivied a small user-only smoke test. I need to build a kernel with the right patches in order to both test this in system mode as well as verify the hashes that I am producing vs ARM Fast Model. However, $ aarch64-linux-gcc-8.0.1 -msign-return-address=all z.c $ ./aarch64-linux-user/qemu-aarch64 -D z -d in_asm,op,cpu -singlestep ./a.out Hello, World! IN: main 0x004005a4: d503233f hint #0x19 OP: ld_i32 tmp0,env,$0xffffffffffffffe4 movi_i32 tmp1,$0x0 brcond_i32 tmp0,tmp1,lt,$L0 ---- 00000000004005a4 0000000000000000 0000000000000000 call pacia,$0x20,$1,lr,env,lr,sp goto_tb $0x1 movi_i64 pc,$0x4005a8 exit_tb $0x5608e569e281 set_label $L0 exit_tb $0x5608e569e283 - X29=00000040007ff4a0 X30=00000040008778a4 SP=00000040007ff4a0 + X29=00000040007ff4a0 X30=c0270040008778a4 SP=00000040007ff4a0 IN: main 0x004005c4: d50323bf hint #0x1d OP: ld_i32 tmp0,env,$0xffffffffffffffe4 movi_i32 tmp1,$0x0 brcond_i32 tmp0,tmp1,lt,$L0 ---- 00000000004005c4 0000000000000000 0000000000000000 call autia,$0x20,$1,lr,env,lr,sp goto_tb $0x1 movi_i64 pc,$0x4005c8 exit_tb $0x5608e5706241 set_label $L0 exit_tb $0x5608e5706243 - X29=00000040007ff4a0 X30=c0270040008778a4 SP=00000040007ff4a0 + X29=00000040007ff4a0 X30=00000040008778a4 SP=00000040007ff4a0 So, yay! We sign something with high bits set and can get back the original pointer. Note that this is with key==0, as I do not yet initialize AutKeyIA to anything, as the real kernel would for a given thread. This is based on my v3 ARMv8.1-LOR patches, which in turn are based on Peter's target-arm.next. The full tree is available at https://github.com/rth7680/qemu.git tgt-arm-pauth and this version is tagged tgt-arm-pauth-hello-world. ;-) r~ Richard Henderson (26): target/arm: Add state for the ARMv8.3-PAuth extension target/arm: Add SCTLR bits through ARMv8.5 target/arm: Add PAuth active bit to tbflags target/arm: Add PAuth helpers target/arm: Decode PAuth within system hint space target/arm: Rearrange decode in disas_data_proc_1src target/arm: Decode PAuth within disas_data_proc_1src target/arm: Decode PAuth within disas_data_proc_2src target/arm: Move helper_exception_return to helper-a64.c target/arm: Add new_pc argument to helper_exception_return target/arm: Rearrange decode in disas_uncond_b_reg target/arm: Decode PAuth within disas_uncond_b_reg target/arm: Decode Load/store register (pac) target/arm: Move cpu_mmu_index out of line target/arm: Introduce arm_mmu_idx target/arm: Create ARMVAParameters and helpers target/arm: Reuse aa64_va_parameters for setting tbflags target/arm: Export aa64_va_parameters to internals.h target/arm: Implement pauth_strip target/arm: Implement pauth_auth target/arm: Implement pauth_addpac target/arm: Implement pauth_computepac target/arm: Add PAuth system registers target/arm: Enable PAuth for user-only -cpu max target/arm: Enable PAuth for user-only, part 2 target/arm: Tidy TBI handling in gen_a64_set_pc target/arm/cpu.h | 151 ++++----- target/arm/helper-a64.h | 14 + target/arm/helper.h | 1 - target/arm/internals.h | 35 ++ target/arm/translate.h | 2 + target/arm/cpu.c | 6 + target/arm/cpu64.c | 4 + target/arm/helper-a64.c | 631 +++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 459 ++++++++++++++++----------- target/arm/machine.c | 23 ++ target/arm/op_helper.c | 155 --------- target/arm/translate-a64.c | 531 ++++++++++++++++++++++++++----- 12 files changed, 1519 insertions(+), 493 deletions(-) -- 2.17.2