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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id q24-v6sm25609327pff.83.2018.10.18.23.06.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 23:06:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 23:06:35 -0700 Message-Id: <20181019060656.7968-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::631 Subject: [Qemu-devel] [PULL v2 00/21] tcg patch queue X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Changes since v1: * Added QEMU_ERROR to wrap __attribute__((error)) -- patch 12. r~ The following changes since commit 77f7c747193662edfadeeb3118d63eed0eac51a6: Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2018-10-17' into staging (2018-10-18 13:40:19 +0100) are available in the Git repository at: https://github.com/rth7680/qemu.git tags/pull-tcg-20181018 for you to fetch changes up to 403f290c0603f35f2d09c982bf5549b6d0803ec1: cputlb: read CPUTLBEntry.addr_write atomically (2018-10-18 19:46:53 -0700) ---------------------------------------------------------------- Queued tcg patches. ---------------------------------------------------------------- Emilio G. Cota (10): tcg: access cpu->icount_decr.u16.high with atomics tcg: fix use of uninitialized variable under CONFIG_PROFILER tcg: plug holes in struct TCGProfile tcg: distribute tcg_time into TCG contexts target/alpha: remove tlb_flush from alpha_cpu_initfn target/unicore32: remove tlb_flush from uc32_init_fn exec: introduce tlb_init cputlb: fix assert_cpu_is_self macro cputlb: serialize tlb updates with env->tlb_lock cputlb: read CPUTLBEntry.addr_write atomically Richard Henderson (11): tcg: Implement CPU_LOG_TB_NOCHAIN during expansion tcg: Add tlb_index and tlb_entry helpers tcg: Split CONFIG_ATOMIC128 target/i386: Convert to HAVE_CMPXCHG128 target/arm: Convert to HAVE_CMPXCHG128 target/arm: Check HAVE_CMPXCHG128 at translate time target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 target/s390x: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 target/s390x: Split do_cdsg, do_lpq, do_stpq target/s390x: Skip wout, cout helpers if op helper does not return target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate accel/tcg/atomic_template.h | 20 +++- accel/tcg/softmmu_template.h | 64 +++++----- include/exec/cpu-defs.h | 3 + include/exec/cpu_ldst.h | 30 ++++- include/exec/cpu_ldst_template.h | 25 ++-- include/exec/exec-all.h | 8 ++ include/qemu/atomic128.h | 153 ++++++++++++++++++++++++ include/qemu/compiler.h | 11 ++ include/qemu/timer.h | 1 - target/ppc/helper.h | 2 +- tcg/tcg.h | 20 ++-- accel/tcg/cpu-exec.c | 2 +- accel/tcg/cputlb.c | 235 +++++++++++++++++++----------------- accel/tcg/tcg-all.c | 2 +- accel/tcg/translate-all.c | 2 +- accel/tcg/user-exec.c | 5 +- cpus.c | 3 +- exec.c | 1 + monitor.c | 13 +- qom/cpu.c | 2 +- target/alpha/cpu.c | 1 - target/arm/helper-a64.c | 251 +++++++++++++++++++-------------------- target/arm/translate-a64.c | 38 +++--- target/i386/mem_helper.c | 9 +- target/ppc/mem_helper.c | 33 ++++- target/ppc/translate.c | 115 +++++++++--------- target/s390x/mem_helper.c | 202 +++++++++++++++---------------- target/s390x/translate.c | 45 +++++-- target/unicore32/cpu.c | 2 - tcg/tcg-op.c | 9 +- tcg/tcg.c | 25 +++- configure | 19 +++ 32 files changed, 839 insertions(+), 512 deletions(-) create mode 100644 include/qemu/atomic128.h