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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id q19-v6sm15071915pff.9.2018.06.29.17.02.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 29 Jun 2018 17:02:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 29 Jun 2018 17:02:40 -0700 Message-Id: <20180630000242.29594-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH 0/2] Fix qemu-system-aarch64 crash X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The sequence of events was (1) Kernel executed a disabled sve insn, (2) Undefined Instruction trap went to EL3, (3) Lookup of the exception handler saw el3 and returned asidx 1, (4) Which hadn't been set up. So there's definitely a bug with SVE exception routing. That said... With just the first patch, the kernel goes into a silly exception loop which is understandable. With just the second patch, qemu gets SIGABRT instead of SIGSEGV, which is definitely easier to debug. I think I'm in favor of both patches, but you might say we shouldn't have to have the first one and just apply the second. r~ Richard Henderson (2): target/arm: Always return ARMASIdx_NS when num_ases == 1 cpu: Assert asidx_from_attrs return value in range include/qom/cpu.h | 6 ++++-- target/arm/cpu.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) -- 2.17.1