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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id j1-v6sm6640418pfc.159.2018.05.16.15.30.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 15:30:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 15:29:40 -0700 Message-Id: <20180516223007.10256-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::229 Subject: [Qemu-devel] [PATCH v3-a 00/27] target/arm: Scalable Vector Extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the first third, more or less, of my current patch set. I'm sending only this portion now, rather than another monster set all at once. The major change is to move the call to sve_access_check inside any final decode reject that might be required. There are other minor cleanups to patch integrity and comments. The changes are mostly trivial from the February v2 patch set, so if an R-b was given, I have retained it. That leaves 4, 7, 8, and 26 (new) as unreviewed. The patch that enables SVE for aarch64-linux-user is not present. r~ Richard Henderson (27): target/arm: Introduce translate-a64.h target/arm: Add SVE decode skeleton target/arm: Implement SVE Bitwise Logical - Unpredicated Group target/arm: Implement SVE load vector/predicate target/arm: Implement SVE predicate test target/arm: Implement SVE Predicate Logical Operations Group target/arm: Implement SVE Predicate Misc Group target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group target/arm: Implement SVE Integer Reduction Group target/arm: Implement SVE bitwise shift by immediate (predicated) target/arm: Implement SVE bitwise shift by vector (predicated) target/arm: Implement SVE bitwise shift by wide elements (predicated) target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group target/arm: Implement SVE Integer Multiply-Add Group target/arm: Implement SVE Integer Arithmetic - Unpredicated Group target/arm: Implement SVE Index Generation Group target/arm: Implement SVE Stack Allocation Group target/arm: Implement SVE Bitwise Shift - Unpredicated Group target/arm: Implement SVE Compute Vector Address Group target/arm: Implement SVE floating-point exponential accelerator target/arm: Implement SVE floating-point trig select coefficient target/arm: Implement SVE Element Count Group target/arm: Implement SVE Bitwise Immediate Group target/arm: Implement SVE Integer Wide Immediate - Predicated Group target/arm: Implement SVE Permute - Extract Group target/arm: Extend vec_reg_offset to larger sizes target/arm: Implement SVE Permute - Unpredicated Group target/arm/cpu.h | 8 +- target/arm/helper-sve.h | 450 ++++++++ target/arm/helper.h | 1 + target/arm/translate-a64.h | 118 ++ target/arm/sve_helper.c | 1676 +++++++++++++++++++++++++++ target/arm/translate-a64.c | 119 +- target/arm/translate-sve.c | 2203 ++++++++++++++++++++++++++++++++++++ .gitignore | 1 + target/arm/Makefile.objs | 10 + target/arm/sve.decode | 446 ++++++++ 10 files changed, 4933 insertions(+), 99 deletions(-) create mode 100644 target/arm/helper-sve.h create mode 100644 target/arm/translate-a64.h create mode 100644 target/arm/sve_helper.c create mode 100644 target/arm/translate-sve.c create mode 100644 target/arm/sve.decode -- 2.17.0