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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:11:51 -0700 Message-Id: <20180514221219.7091-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v5 00/28] softfloat patch roundup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is my SNaN patch set, Alex's float-float refactor, and a couple of other random outstanding fpu patches. This has been reordered so as to be bisectable, since the float-float refactor requires the snan work to avoid breakage. This was built on top of pm215/target-arm.next to make it easier to test. The whole tree is git://github.com/rth7680/qemu.git fpu-roundup Changes since last: - Use v5 instead of v3, since Alex was up to v4 with float-float. - Incorporate feedback from pm215. - Include float128 fix from Petr. - Include further cleanups for default_nan and silence_nan. The first of these was inspired by a comment from pm215; the rest follow as logical extensions. r~ Alex Bennée (4): target/arm: convert conversion helpers to fpst/ahp_flag target/arm: squash FZ16 behaviour for conversions fpu/softfloat: Partial support for ARM Alternative half-precision fpu/softfloat: re-factor float to float conversions Petr Tesarik (1): fpu/softfloat: Fix conversion from uint64 to float128 Richard Henderson (23): fpu/softfloat: Merge NO_SIGNALING_NANS definitions fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan fpu/softfloat: Move softfloat-specialize.h below FloatParts definition fpu/softfloat: Canonicalize NaN fraction fpu/softfloat: Introduce parts_is_snan_frac fpu/softfloat: Replace float_class_dnan with parts_default_nan fpu/softfloat: Replace float_class_msnan with parts_silence_nan target/arm: Use floatX_silence_nan when we have already checked for SNaN target/arm: Remove floatX_maybe_silence_nan from conversions target/hppa: Remove floatX_maybe_silence_nan from conversions target/m68k: Use floatX_silence_nan when we have already checked for SNaN target/mips: Remove floatX_maybe_silence_nan from conversions target/riscv: Remove floatX_maybe_silence_nan from conversions target/s390x: Remove floatX_maybe_silence_nan from conversions fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN fpu/softfloat: Remove floatX_maybe_silence_nan fpu/softfloat: Specialize on snan_bit_is_one fpu/softfloat: Make is_nan et al available to softfloat-specialize.h fpu/softfloat: Pass FloatClass to pickNaN fpu/softfloat: Pass FloatClass to pickNaNMulAdd fpu/softfloat: Define floatN_default_nan in terms of parts_default_nan fpu/softfloat: Clean up parts_default_nan fpu/softfloat: Define floatN_silence_nan in terms of parts_silence_nan fpu/softfloat-specialize.h | 691 ++++++++++++++------------------- include/fpu/softfloat-types.h | 1 + include/fpu/softfloat.h | 18 +- target/arm/helper.h | 10 +- target/arm/translate.h | 12 + fpu/softfloat.c | 708 ++++++++++++---------------------- target/arm/helper-a64.c | 7 +- target/arm/helper.c | 114 +++--- target/arm/translate-a64.c | 38 +- target/arm/translate.c | 74 +++- target/hppa/cpu.c | 1 - target/hppa/op_helper.c | 2 - target/m68k/softfloat.c | 3 +- target/mips/msa_helper.c | 4 - target/mips/op_helper.c | 2 - target/ppc/fpu_helper.c | 1 - target/riscv/fpu_helper.c | 6 +- target/s390x/fpu_helper.c | 12 +- target/sh4/cpu.c | 1 - target/unicore32/cpu.c | 2 - 20 files changed, 701 insertions(+), 1006 deletions(-) -- 2.17.0 Tested-by: Alex Bennée