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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id k84-v6sm10756406pfh.93.2018.05.11.17.43.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 17:43:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 17:42:44 -0700 Message-Id: <20180512004311.9299-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 00/27] softfloat patch roundup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is my SNaN patch set, Alex's float-float refactor, and a couple of other random outstanding fpu patches. This has been reordered so as to be bisectable, since the float-float refactor requires the snan work to avoid breakage. It probably doesn't matter, but this was built on top of my arm fp16 patch set simply to make it easier to test. The whole tree is git://github.com/rth7680/qemu.git fpu-roundup r~ Alex Bennée (5): fpu/softfloat: int_to_float ensure r fully initialised fpu/softfloat: re-factor float to float conversions fpu/softfloat: support ARM Alternative half-precision target/arm: convert conversion helpers to fpst/ahp_flag target/arm: squash FZ16 behaviour for conversions Peter Maydell (2): fpu/softfloat: Don't set Invalid for float-to-int(MAXINT) target/arm: Fix fp_status_f16 tininess before rounding Richard Henderson (20): fpu/softfloat: Merge NO_SIGNALING_NANS definitions fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan fpu/softfloat: Move softfloat-specialize.h below FloatParts definition fpu/softfloat: Canonicalize NaN fraction fpu/softfloat: Introduce parts_is_snan_frac fpu/softfloat: Replace float_class_dnan with parts_default_nan fpu/softfloat: Replace float_class_msnan with parts_silence_nan target/arm: Use floatX_silence_nan when we have already checked for SNaN target/arm: Remove floatX_maybe_silence_nan from conversions target/hppa: Remove floatX_maybe_silence_nan from conversions target/m68k: Use floatX_silence_nan when we have already checked for SNaN target/mips: Remove floatX_maybe_silence_nan from conversions target/riscv: Remove floatX_maybe_silence_nan from conversions target/s390x: Remove floatX_maybe_silence_nan from conversions fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN fpu/softfloat: Remove floatX_maybe_silence_nan fpu/softfloat: Specialize on snan_bit_is_one fpu/softfloat: Make is_nan et al available to softfloat-specialize.h fpu/softfloat: Pass FloatClass to pickNaN fpu/softfloat: Pass FloatClass to pickNaNMulAdd fpu/softfloat-specialize.h | 668 ++++++++++++++++++---------------- include/fpu/softfloat-types.h | 1 + include/fpu/softfloat.h | 22 +- target/arm/helper.h | 10 +- target/arm/translate.h | 12 + target/mips/cpu.h | 4 +- fpu/softfloat.c | 665 ++++++++++----------------------- target/arm/cpu.c | 2 + target/arm/helper-a64.c | 7 +- target/arm/helper.c | 114 +++--- target/arm/translate-a64.c | 38 +- target/arm/translate.c | 74 +++- target/hppa/cpu.c | 1 - target/hppa/op_helper.c | 2 - target/m68k/softfloat.c | 3 +- target/mips/msa_helper.c | 4 - target/mips/op_helper.c | 2 - target/mips/translate_init.c | 4 +- target/ppc/fpu_helper.c | 1 - target/riscv/fpu_helper.c | 6 +- target/s390x/fpu_helper.c | 12 +- target/sh4/cpu.c | 1 - target/unicore32/cpu.c | 2 - 23 files changed, 730 insertions(+), 925 deletions(-) -- 2.17.0