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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id p184si214315ywh.791.2018.02.07.03.20.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 07 Feb 2018 03:20:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KRsTOhqo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51704 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejNmT-0006e3-Cs for patch@linaro.org; Wed, 07 Feb 2018 06:20:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38753) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejNjU-0005DJ-7s for qemu-devel@nongnu.org; Wed, 07 Feb 2018 06:17:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejNjP-0005d2-Al for qemu-devel@nongnu.org; Wed, 07 Feb 2018 06:17:44 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:56169) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ejNjP-0005cb-2m for qemu-devel@nongnu.org; Wed, 07 Feb 2018 06:17:39 -0500 Received: by mail-wm0-x242.google.com with SMTP id 143so2415854wma.5 for ; Wed, 07 Feb 2018 03:17:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=FnhCOBqehV6C8RVrX2oXL2RNy5ExGduk3Vpt8gk6lxw=; b=KRsTOhqoWbao8eOApzOQ8/4A2PPpzwA3KV/OEQiLWvCv/5seaqyaYhbtvAfKZeqRdD R+9gEqH0vBms0jbHKqBHl1PUPGQ8lvHEI+PUoc5IGJPV5lesjuEr9tcNyc0mU+P03mgQ DMI462E1EK7i9s2JzSLXkckw3ydz3f+j5cxTI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=FnhCOBqehV6C8RVrX2oXL2RNy5ExGduk3Vpt8gk6lxw=; b=AWMO+76FIpAfe0JZ8l4SdqcV6cpisd4v43qPJlfUEswQUKhAOOWFWB4Q5dIW6X2y9d 1eQQdfNFXyi8Hcn/Khpi3zy604+oy5t5BVlm6gn9H/1bKqUVA25uT3jWJG7CBg+dzQ/F wsaC88Qk4Qccz5g9QJf1XhRKf4WdMpeIaKJQYPhhdWeNxSax+yFrGJUrkKeu1fkBy2Zf 278ixP9rnPJNhu0Gl6RixjGuGVDA/PAbCMe7tvvf4GICDZWH2tGA4jEbQqliVCphxxsD jYopeIUZePn7K/u7rotaOU6RnewuBs3VWLCVVFs5QRSTKGNxxio/imHy2FBH4HcYXcqY Fh5g== X-Gm-Message-State: APf1xPD3l+y3nrC0AM5+9HfBqYiRu09Rr2rdh9ysAv14XUiyMkpNS0Yt u88gA6kveLUQ41anuRoqfawTGU6RKPc= X-Received: by 10.28.106.26 with SMTP id f26mr4265668wmc.36.1518002257658; Wed, 07 Feb 2018 03:17:37 -0800 (PST) Received: from localhost.localdomain ([196.85.252.149]) by smtp.gmail.com with ESMTPSA id h32sm627629wrf.65.2018.02.07.03.17.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Feb 2018 03:17:36 -0800 (PST) From: Ard Biesheuvel To: qemu-devel@nongnu.org Date: Wed, 7 Feb 2018 11:17:24 +0000 Message-Id: <20180207111729.15737-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v6 0/5] target-arm: add SHA-3, SM3 and SHA512 instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Changes since v5: - fix use of same register for destination and source in SHA-512 code - use correct free() function in SHA-3 code - drop helper for sm3ss1 in SM3 code - include fixed version of SM4 (correct # of iterations) - enable SM4 in user mode emulator Changes since v4: - restructure code changes to make it easier on the reviewer - add Peter's R-b to #4 Changes since v3: - don't bother with helpers for the SHA3 instructions: they are simple enough to be emitted as TCG ops directly - rebase onto Richard's pending SVE work Changes since v2: - fix thinko in big-endian aware handling of 64-bit quantities: this is not needed given that the NEON registers are represented as arrays of uint64_t so they always appear in the correct order. - add support for SM3 instructions (Chinese SHA derivative) Changes since v1: - update SHA512 patch to adhere more closely to the existing style, and to the way the instruction encodings are classified in the ARM ARM (#1) - add patch implementing the new SHA3 instructions EOR3/RAX1/XAR/BCAX (#2) - enable support for these instructions in user mode emulation (#3) Ard Biesheuvel (5): target/arm: implement SHA-512 instructions target/arm: implement SHA-3 instructions target/arm: implement SM3 instructions target/arm: implement SM4 instructions target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support linux-user/elfload.c | 19 ++ target/arm/cpu.h | 4 + target/arm/cpu64.c | 4 + target/arm/crypto_helper.c | 277 +++++++++++++++- target/arm/helper.h | 12 + target/arm/translate-a64.c | 340 ++++++++++++++++++++ 6 files changed, 655 insertions(+), 1 deletion(-) -- 2.11.0