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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id m10sm9260469pgs.4.2017.12.18.09.24.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:24:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:24:14 -0800 Message-Id: <20171218172425.18200-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PATCH v2 00/11] ARM v8.1 simd + v8.3 complex insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" I've incorporated Alex's feedback from v1, and have now rebased upon Alex's work so that the complex insns now support fp16. r~ Richard Henderson (11): target/arm: Add ARM_FEATURE_V8_1_SIMD target/arm: Decode aa64 armv8.1 scalar three same extra target/arm: Decode aa64 armv8.1 three same extra target/arm: Decode aa64 armv8.1 scalar/vector x indexed element target/arm: Decode aa32 armv8.1 three same target/arm: Decode aa32 armv8.1 two reg and a scalar target/arm: Add ARM_FEATURE_V8_FCMA target/arm: Decode aa64 armv8.3 fcadd target/arm: Decode aa64 armv8.3 fcmla target/arm: Decode aa32 armv8.3 3-same target/arm: Decode aa32 armv8.3 2-reg-index target/arm/cpu.h | 2 + target/arm/helper.h | 31 ++++ linux-user/elfload.c | 10 ++ target/arm/advsimd_helper.c | 420 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 2 + target/arm/cpu64.c | 2 + target/arm/translate-a64.c | 382 ++++++++++++++++++++++++++++++++++++---- target/arm/translate.c | 239 ++++++++++++++++++++++--- target/arm/Makefile.objs | 2 +- 9 files changed, 1032 insertions(+), 58 deletions(-) create mode 100644 target/arm/advsimd_helper.c -- 2.14.3