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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id d123si1379363qkg.185.2017.02.22.09.33.26 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 22 Feb 2017 09:33:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54294 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgan6-000092-GD for patch@linaro.org; Wed, 22 Feb 2017 12:33:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35487) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgaTk-0006cI-4M for qemu-devel@nongnu.org; Wed, 22 Feb 2017 12:13:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cgaTh-0000TV-HA for qemu-devel@nongnu.org; Wed, 22 Feb 2017 12:13:24 -0500 Received: from mail-wr0-x229.google.com ([2a00:1450:400c:c0c::229]:32955) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cgaTh-0000TO-7K for qemu-devel@nongnu.org; Wed, 22 Feb 2017 12:13:21 -0500 Received: by mail-wr0-x229.google.com with SMTP id 97so6628136wrb.0 for ; Wed, 22 Feb 2017 09:13:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=9nrbJgXOMciqcR4SbGFZL9Pn5tPvHvaQHDzIkhUoWz4=; b=PUiEJc3bEQE/ICujuaAWeCDSJzjNXNnbr6//n/WaSJVJX8yuTpYjczPDpoi54vZU6H MnDmoGit78G3u5OFqPhpgUSVBsDapzETjjrfJ8Af4LfvolZXmop4jg5PRlswt/djKniE Rk2nAorPbmSFQS+DgbksOp2om1KhutKQJwe30= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=9nrbJgXOMciqcR4SbGFZL9Pn5tPvHvaQHDzIkhUoWz4=; b=S3uVTi7eVdjxZMUKkNDb47LGLY7CiQ/bqqnC8GW7PnX0VmRCW9q45+v8w+xMfw977F PfwQsZlm4ZI0PxCJyPzVckxkopESOQt5ZCpeu+xl/LUqlLTsvacHZuwcEOZE9njWrcwj TpNnyJ8aUeGO0dp57++kG132VeT7U2HPNytfYfLDsMmRCrEk9f+/Og871IWQoSko2PFs znTW6djTLnqDI7quDEBBiCxPReBEb9ZDjBwgRuSZA1ZHuEq+qR7l2/6NFwhcTA1sY1GR SDAZ2HxaBv31vmAdufoVtaEU3JNTUvhdJbvs/BElyczLUx6Wd20B0pCZx2mPDqzdCbFg zZ/g== X-Gm-Message-State: AMke39nx//k1OA2q5I3D1g7+rCuavNcHkgn9wP1uE4TRyDIByUyP8yHRNXLJQDibRwgvgdtE X-Received: by 10.223.165.70 with SMTP id j6mr12199204wrb.173.1487783599824; Wed, 22 Feb 2017 09:13:19 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id m29sm2481167wrm.38.2017.02.22.09.13.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Feb 2017 09:13:18 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id AC1A43E014D; Wed, 22 Feb 2017 17:13:27 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: rth@twiddle.net, peter.maydell@linaro.org Date: Wed, 22 Feb 2017 17:13:03 +0000 Message-Id: <20170222171327.26624-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c0c::229 Subject: [Qemu-devel] [PATCH v13 00/24] MTTCG Base enabling patches with ARM enablement X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, nikunj@linux.vnet.ibm.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, serge.fdrv@gmail.com, pbonzini@redhat.com, bobby.prani@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hi Richard/Peter, I'm hoping this is the final version and we are ready to submit a pull-request to merge MTTCG upstream. Apart from the final set of architecture reviewed-by's the following patches have had minor tweaks: tcg: handle EXCP_ATOMIC exception for system emulation Fixed to handle yet another corner case of tb-flush being triggered during an EXCP_ATOMIC exceptions. Also the mmap_lock is now correctly taken (as EXCP_ATOMIC can be taken for linux-user). tcg: remove global exit_request In the single threaded round robin we also check for cpu->queued_work_first and bail the loop if needed. Otherwise we run into strangeness when the "target-arm: ensure all cross vCPUs TLB flushes complete" runs in single-threaded mode. The tail end of the commit message has been tweaked to explain this. tcg: enable thread-per-vCPU Pranith found a regression running linux-user tests/atomic_bench which was due to the fact we previously removed a setting of cpu->exit_request to 0 in cpu_handle_interrupt. Because the linux-user loop doesn't have the outer loop of system emulation this caused it to hang - always exiting the TB. There was a knock on effect w.r.t to safe work for single-threaded execution but this was fixed in commit above. So if you are happy are you going to be able to submit the pull request before the soft-freeze kicks in? Regards, Alex. Alex Bennée (18): docs: new design document multi-thread-tcg.txt tcg: move TCG_MO/BAR types into own file tcg: add kick timer for single-threaded vCPU emulation tcg: rename tcg_current_cpu to tcg_current_rr_cpu tcg: remove global exit_request tcg: enable tb_lock() for SoftMMU tcg: enable thread-per-vCPU cputlb: add assert_cpu_is_self checks cputlb: tweak qemu_ram_addr_from_host_nofail reporting cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap cputlb: add tlb_flush_by_mmuidx async routines cputlb: atomically update tlb fields used by tlb_reset_dirty cputlb: introduce tlb_flush_*_all_cpus[_synced] target-arm/powerctl: defer cpu reset work to CPU context target-arm: don't generate WFE/YIELD calls for MTTCG target-arm: ensure all cross vCPUs TLB flushes complete hw/misc/imx6_src: defer clearing of SRC_SCR reset bits tcg: enable MTTCG by default for ARM on x86 hosts Jan Kiszka (1): tcg: drop global lock during TCG code execution KONRAD Frederic (2): tcg: add options for enabling MTTCG cputlb: introduce tlb_flush_* async work. Pranith Kumar (3): mttcg: translate-all: Enable locking debug in a debug build mttcg: Add missing tb_lock/unlock() in cpu_exec_step() tcg: handle EXCP_ATOMIC exception for system emulation configure | 6 + cpu-exec-common.c | 3 - cpu-exec.c | 85 ++++++--- cpus.c | 345 ++++++++++++++++++++++++++------- cputlb.c | 463 +++++++++++++++++++++++++++++++++++++-------- docs/multi-thread-tcg.txt | 350 ++++++++++++++++++++++++++++++++++ exec.c | 12 +- hw/core/irq.c | 1 + hw/i386/kvmvapic.c | 4 +- hw/intc/arm_gicv3_cpuif.c | 3 + hw/misc/imx6_src.c | 58 +++++- hw/ppc/ppc.c | 16 +- hw/ppc/spapr.c | 3 + include/exec/cputlb.h | 2 - include/exec/exec-all.h | 132 +++++++++++-- include/qom/cpu.h | 16 ++ include/sysemu/cpus.h | 2 + memory.c | 2 + qemu-options.hx | 20 ++ qom/cpu.c | 10 + target/arm/arm-powerctl.c | 202 +++++++++++++------- target/arm/arm-powerctl.h | 2 + target/arm/cpu.c | 4 +- target/arm/cpu.h | 18 +- target/arm/helper.c | 219 ++++++++++----------- target/arm/kvm.c | 7 +- target/arm/machine.c | 41 +++- target/arm/op_helper.c | 50 ++++- target/arm/psci.c | 4 +- target/arm/translate-a64.c | 8 +- target/arm/translate.c | 20 +- target/i386/smm_helper.c | 7 + target/s390x/misc_helper.c | 5 +- target/sparc/ldst_helper.c | 8 +- tcg/i386/tcg-target.h | 11 ++ tcg/tcg-mo.h | 48 +++++ tcg/tcg.h | 27 +-- translate-all.c | 66 ++----- translate-common.c | 21 +- vl.c | 49 ++++- 40 files changed, 1874 insertions(+), 476 deletions(-) create mode 100644 docs/multi-thread-tcg.txt create mode 100644 tcg/tcg-mo.h -- 2.11.0