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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id v13si7104021qta.74.2017.02.13.04.19.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 13 Feb 2017 04:19:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56205 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdFbh-00058S-AH for patch@linaro.org; Mon, 13 Feb 2017 07:19:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdFSI-0005Ay-8K for qemu-devel@nongnu.org; Mon, 13 Feb 2017 07:10:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cdFSE-0002VN-80 for qemu-devel@nongnu.org; Mon, 13 Feb 2017 07:10:06 -0500 Received: from mail-wm0-x231.google.com ([2a00:1450:400c:c09::231]:35606) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cdFSE-0002Ui-03 for qemu-devel@nongnu.org; Mon, 13 Feb 2017 07:10:02 -0500 Received: by mail-wm0-x231.google.com with SMTP id v186so156313072wmd.0 for ; Mon, 13 Feb 2017 04:10:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4Sltqi6+TITpRXArSuRt2E11V0q23y3iF3ZFN9bo3UY=; b=Dyow9Zsn8aJxYk59HWQ6rlR2XhmtLOjN3p71xr3byrAMo2/wVltiT7uRH5sZ3rwNwP 3ZToIVzXcxulqOQLMv8WjG+lQu4fDOP/7KjYd8NmfhZ6pXi79Llfw2fUElJYEFizR6MH SRW2CuSJ2e7yprYc9rS4qgkWhEaM4n6GFHqPg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4Sltqi6+TITpRXArSuRt2E11V0q23y3iF3ZFN9bo3UY=; b=AUNN/c+p+Rf7dgKow29tC9P6rpewrQOYgLh771oF2QsQlwQ0pfc7FlWCiNkQv0DJbM T+RoK1CEVAWAA/Zy7SfLBHQ1jDUnmUAYlRfBb8V6i/gt8Gi4lKb6+km32HV+XYz0p4Pv txycn977P5kIvH+VIUyO29va4L0YTRMR4w122k2RKGzxfSH1Ep9bxuw5oH/a0b5W4Ym5 sfl2m4emZZ7Fe/h6BMYiGPSejoXS+tItuzuxFDsJCHxxPv/NRlZQSVJjlvwHk8FAsapg sf17SI9NRlF5XBkLW126nRLMrPeT5FwLB0ejIIYH+MVX1wHm7TF86hBKZnBrREDkt5ya rkgg== X-Gm-Message-State: AMke39mO2x06VUVx2uRyTSpbE6srJ6tEhy9J7lxY2/gRNplgFtrsHwfTfDBVDliub1lK/2TZ X-Received: by 10.28.62.144 with SMTP id l138mr17981419wma.50.1486987799156; Mon, 13 Feb 2017 04:09:59 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id s26sm13592319wra.26.2017.02.13.04.09.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Feb 2017 04:09:58 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 21C083E0199; Mon, 13 Feb 2017 12:10:17 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org, rth@twiddle.net Date: Mon, 13 Feb 2017 12:09:53 +0000 Message-Id: <20170213121017.12907-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::231 Subject: [Qemu-devel] [PATCH v12 00/24] MTTCG Base enabling patches with ARM enablement X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, nikunj@linux.vnet.ibm.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, serge.fdrv@gmail.com, pbonzini@redhat.com, bobby.prani@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hi Richard/Peter, Only a few changes from the last posting. There were a couple of tweaks to the ARM powerctl patches to address review comments. I've also folded the patches from Pranith: Subject: [PATCH v2 0/2] mttcg: Handle exception and flags in atomic execution Date: Fri, 10 Feb 2017 13:45:23 -0500 Message-Id: <20170210184525.10966-1-bobby.prani@gmail.com> Into: tcg: handle EXCP_ATOMIC exception for system emulation This fixes up EXCP_ATOMIC handling so you can single-step through emulated atomics. I tested this by manually tweaking the #ifdef ATOMIC_64 and ATOMIC_128 bits in target/i386/mem_helper.c. As it changes the code a bit I've set Richard's review-by to pending until he can ack the changes. Regards, Alex Alex Bennée (18): docs: new design document multi-thread-tcg.txt tcg: move TCG_MO/BAR types into own file tcg: add kick timer for single-threaded vCPU emulation tcg: rename tcg_current_cpu to tcg_current_rr_cpu tcg: remove global exit_request tcg: enable tb_lock() for SoftMMU tcg: enable thread-per-vCPU cputlb: add assert_cpu_is_self checks cputlb: tweak qemu_ram_addr_from_host_nofail reporting cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap cputlb: add tlb_flush_by_mmuidx async routines cputlb: atomically update tlb fields used by tlb_reset_dirty cputlb: introduce tlb_flush_*_all_cpus[_synced] target-arm/powerctl: defer cpu reset work to CPU context target-arm: don't generate WFE/YIELD calls for MTTCG target-arm: ensure all cross vCPUs TLB flushes complete hw/misc/imx6_src: defer clearing of SRC_SCR reset bits tcg: enable MTTCG by default for ARM on x86 hosts Jan Kiszka (1): tcg: drop global lock during TCG code execution KONRAD Frederic (2): tcg: add options for enabling MTTCG cputlb: introduce tlb_flush_* async work. Pranith Kumar (3): mttcg: translate-all: Enable locking debug in a debug build mttcg: Add missing tb_lock/unlock() in cpu_exec_step() tcg: handle EXCP_ATOMIC exception for system emulation configure | 6 + cpu-exec-common.c | 3 - cpu-exec.c | 55 ++++-- cpus.c | 344 ++++++++++++++++++++++++++------- cputlb.c | 463 +++++++++++++++++++++++++++++++++++++-------- docs/multi-thread-tcg.txt | 350 ++++++++++++++++++++++++++++++++++ exec.c | 12 +- hw/core/irq.c | 1 + hw/i386/kvmvapic.c | 4 +- hw/intc/arm_gicv3_cpuif.c | 3 + hw/misc/imx6_src.c | 58 +++++- hw/ppc/ppc.c | 16 +- hw/ppc/spapr.c | 3 + include/exec/cputlb.h | 2 - include/exec/exec-all.h | 132 +++++++++++-- include/qom/cpu.h | 16 ++ include/sysemu/cpus.h | 2 + memory.c | 2 + qemu-options.hx | 20 ++ qom/cpu.c | 10 + target/arm/arm-powerctl.c | 202 +++++++++++++------- target/arm/arm-powerctl.h | 2 + target/arm/cpu.c | 4 +- target/arm/cpu.h | 18 +- target/arm/helper.c | 219 ++++++++++----------- target/arm/kvm.c | 7 +- target/arm/machine.c | 41 +++- target/arm/op_helper.c | 50 ++++- target/arm/psci.c | 4 +- target/arm/translate-a64.c | 8 +- target/arm/translate.c | 20 +- target/i386/smm_helper.c | 7 + target/s390x/misc_helper.c | 5 +- target/sparc/ldst_helper.c | 8 +- tcg/i386/tcg-target.h | 11 ++ tcg/tcg-mo.h | 48 +++++ tcg/tcg.h | 27 +-- translate-all.c | 66 ++----- translate-common.c | 21 +- vl.c | 49 ++++- 40 files changed, 1853 insertions(+), 466 deletions(-) create mode 100644 docs/multi-thread-tcg.txt create mode 100644 tcg/tcg-mo.h -- 2.11.0