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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id r186si8475736qke.184.2017.02.09.09.24.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 09 Feb 2017 09:24:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbsSe-0003Dl-OL for patch@linaro.org; Thu, 09 Feb 2017 12:24:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56661) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbsDL-0006Bj-4u for qemu-devel@nongnu.org; Thu, 09 Feb 2017 12:09:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbsDG-0002MJ-4p for qemu-devel@nongnu.org; Thu, 09 Feb 2017 12:08:59 -0500 Received: from mail-wm0-x229.google.com ([2a00:1450:400c:c09::229]:37439) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cbsDF-0002Ld-TK for qemu-devel@nongnu.org; Thu, 09 Feb 2017 12:08:54 -0500 Received: by mail-wm0-x229.google.com with SMTP id v77so25861946wmv.0 for ; Thu, 09 Feb 2017 09:08:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=yqUEdRRA7+sCVjJjdgz3z3qsUCcrSyjOIfN2D/g8JGo=; b=ZYCmj1Mbd10jgMisRKGKDODJoR3GehUCll+SgCI75Q+ydQ3aCapt/aXumKNdfZ6vHU cDqR7UwRdWKzWm2FnWgVLaqQfl7Z8vqAMBuGjmMJeiFsI6Uu8J3y0AdY8uI7FDqlX5HA dTxUGC/Gq27Y9vGu99DaK/qvzTv0LlWkanoXc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=yqUEdRRA7+sCVjJjdgz3z3qsUCcrSyjOIfN2D/g8JGo=; b=ewGwbqMGLYtAhe2w0H7RFb/eTVmLcmc31aFJYV57WiFAERB9V9q3cd5lZZqfez72xx U5mLUvJIbs3karXxLySTFhmqHVOL6C21++bOY8b8c1T8/T8fJVbA6LZx9vvMSAHQtS78 MPtYieuJZlJTLoA8ZO8/SRG81uF2O+FVpHR+cuVj589+39MNHPY5qEB3mYAUHbtwgCb2 cIKetmue0rPefeP9Slbumx2Ep5GnmC7jsdWCQDP6vivct6h4Wx3TFswLQsOH4qSVazqY rL5iVQ7mr6bTAjWGpb/1+yKE17jJokUKFIfVa0TpKzVfLZEjU7YmoRDG4LenSt3/NT2g iahw== X-Gm-Message-State: AMke39lywB3qze2ejK2/7XQ+xZZGMYqUmG3vLMmTjoglEuBJQYRBMvVkDT7VqOZSIhsQeua4 X-Received: by 10.28.8.213 with SMTP id 204mr4036084wmi.100.1486660132483; Thu, 09 Feb 2017 09:08:52 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 202sm9776219wmp.20.2017.02.09.09.08.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Feb 2017 09:08:51 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id B66AF3E0A9A; Thu, 9 Feb 2017 17:09:04 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org, rth@twiddle.net Date: Thu, 9 Feb 2017 17:08:40 +0000 Message-Id: <20170209170904.5713-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::229 Subject: [Qemu-devel] [PATCH v11 00/24] MTTCG Base enabling patches with ARM enablement X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, nikunj@linux.vnet.ibm.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, serge.fdrv@gmail.com, pbonzini@redhat.com, bobby.prani@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hi Richard/Peter, Again this is an entirely ARM focused update. The changes are: - updates to target-arm/powerctl following review comments - new: fix up the imx6_src reset register handling The imx change is to correctly the model the state of the reset bits in light of the new asynchronous behaviour of ARMs power interface. Otherwise there is the usual selection of review and testing tags including Pranith's which I missed out on last cycle. Regards, Alex Alex Bennée (18): docs: new design document multi-thread-tcg.txt tcg: move TCG_MO/BAR types into own file tcg: add kick timer for single-threaded vCPU emulation tcg: rename tcg_current_cpu to tcg_current_rr_cpu tcg: remove global exit_request tcg: enable tb_lock() for SoftMMU tcg: enable thread-per-vCPU cputlb: add assert_cpu_is_self checks cputlb: tweak qemu_ram_addr_from_host_nofail reporting cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap cputlb: add tlb_flush_by_mmuidx async routines cputlb: atomically update tlb fields used by tlb_reset_dirty cputlb: introduce tlb_flush_*_all_cpus[_synced] target-arm/powerctl: defer cpu reset work to CPU context target-arm: don't generate WFE/YIELD calls for MTTCG target-arm: ensure all cross vCPUs TLB flushes complete hw/misc/imx6_src: defer clearing of SRC_SCR reset bits tcg: enable MTTCG by default for ARM on x86 hosts Jan Kiszka (1): tcg: drop global lock during TCG code execution KONRAD Frederic (2): tcg: add options for enabling MTTCG cputlb: introduce tlb_flush_* async work. Pranith Kumar (3): mttcg: translate-all: Enable locking debug in a debug build mttcg: Add missing tb_lock/unlock() in cpu_exec_step() tcg: handle EXCP_ATOMIC exception for system emulation configure | 6 + cpu-exec-common.c | 3 - cpu-exec.c | 41 ++-- cpus.c | 344 ++++++++++++++++++++++++++------- cputlb.c | 463 +++++++++++++++++++++++++++++++++++++-------- docs/multi-thread-tcg.txt | 350 ++++++++++++++++++++++++++++++++++ exec.c | 12 +- hw/core/irq.c | 1 + hw/i386/kvmvapic.c | 4 +- hw/intc/arm_gicv3_cpuif.c | 3 + hw/misc/imx6_src.c | 58 +++++- hw/ppc/ppc.c | 16 +- hw/ppc/spapr.c | 3 + include/exec/cputlb.h | 2 - include/exec/exec-all.h | 132 +++++++++++-- include/qom/cpu.h | 16 ++ include/sysemu/cpus.h | 2 + memory.c | 2 + qemu-options.hx | 20 ++ qom/cpu.c | 10 + target/arm/arm-powerctl.c | 202 +++++++++++++------- target/arm/arm-powerctl.h | 2 + target/arm/cpu.c | 4 +- target/arm/cpu.h | 16 +- target/arm/helper.c | 219 ++++++++++----------- target/arm/kvm.c | 7 +- target/arm/machine.c | 6 +- target/arm/op_helper.c | 50 ++++- target/arm/psci.c | 16 +- target/arm/translate-a64.c | 8 +- target/arm/translate.c | 20 +- target/i386/smm_helper.c | 7 + target/s390x/misc_helper.c | 5 +- target/sparc/ldst_helper.c | 8 +- tcg/i386/tcg-target.h | 11 ++ tcg/tcg-mo.h | 48 +++++ tcg/tcg.h | 27 +-- translate-all.c | 66 ++----- translate-common.c | 21 +- vl.c | 49 ++++- 40 files changed, 1815 insertions(+), 465 deletions(-) create mode 100644 docs/multi-thread-tcg.txt create mode 100644 tcg/tcg-mo.h -- 2.11.0