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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id n142si14619829qkn.84.2017.02.01.07.08.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 01 Feb 2017 07:08:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51443 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cYwWh-0000Hm-TF for patch@linaro.org; Wed, 01 Feb 2017 10:08:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37062) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cYwTw-00071w-VU for qemu-devel@nongnu.org; Wed, 01 Feb 2017 10:06:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cYwTq-0008B1-PO for qemu-devel@nongnu.org; Wed, 01 Feb 2017 10:06:00 -0500 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:36397) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cYwTq-0008Am-Fs for qemu-devel@nongnu.org; Wed, 01 Feb 2017 10:05:54 -0500 Received: by mail-wm0-x230.google.com with SMTP id c85so43193936wmi.1 for ; Wed, 01 Feb 2017 07:05:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/PPoEWm5uN2v/hrYGaDUIH7u0+fjRLF5fzibn5W1tKQ=; b=W4b4NDC1KxgJA5TaQXlDaM9odEL1uQkFsNNZJ8la2o3pr/+KA6+WJMU/3gO7O/wv1W KYegGml1PYW5EAQD+laZGh4Zt2Au3wExh4PZz9uUaorybM2rav/su31mIDWyu32r9TDh fml5XreKUGbY8Rq96DT9/u8UW/5yvoeE/ShIo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/PPoEWm5uN2v/hrYGaDUIH7u0+fjRLF5fzibn5W1tKQ=; b=RYmC+61yp8iazQYXAZVxx+WaJi1hVKSFbsWNzUar5jPU4hN3zeWzOCYWfPwWH5ludv kO+IuFpluFveFuixlNgIBLmt4KVtJ0OtSStYmNHNCtUVy1JiC5g5oVlZVWr427o7ntvY 36Dpm7rd3AocP7Gj8Oyr5NcOfd8NDcPMLV2u7tQvXYxaHMm0uENaG8XGBZ8jn1tVaWlu Pz4GxCnEMphG7eblBEGBby0XagKzkR9RfFzSDhLw60ZPLEHFWKfOGYCHzpklOOisb4Ee uk6cpV7MwMeW5lsp//b5v4NMbVlYo9EDM0gBUVKqYSc3bZFDh96r/D+lVmCeoU6pm5C1 s80Q== X-Gm-Message-State: AIkVDXI9cm9texIp4Wza3SFsXK9HS4rkeqJCH1Fkv0NLvMx5rK9CrRYPui9/Qpk8yO9n6Y5a X-Received: by 10.28.222.11 with SMTP id v11mr23002070wmg.1.1485961552628; Wed, 01 Feb 2017 07:05:52 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 18sm34541760wrb.14.2017.02.01.07.05.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Feb 2017 07:05:51 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 4C72A3E07AE; Wed, 1 Feb 2017 15:05:53 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com Date: Wed, 1 Feb 2017 15:05:28 +0000 Message-Id: <20170201150553.9381-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [PATCH v9 00/25] MTTCG Base enabling patches with ARM enablement X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, jan.kiszka@siemens.com, mark.burton@greensocs.com, serge.fdrv@gmail.com, pbonzini@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hi, This is a quick update to the series I posted at the end of last week. It mostly adds a bunch of review tags. There are two changes of note: cputlb and arm/sparc targets: convert mmuidx flushes... This has been updated to reduce the churn of the previous iteration by doing all the MMUIdx shifting in-situ for the tlb_flush calls. And: tcg: enable MTTCG by default for ARM on x86 hosts Mostly cosmetic tweaks but I have clarified the semantics of the TCG_MO_foo declarations with a tweak to the TCG_TARGET_DEFAULT_MO on x86 to be (TCG_MO_ALL & ~TCG_MO_ST_LD). >From v8 rth said: "As far as I'm concerned, I'm done with my review and this can go in." So this is really your last chance to raise any concerns or questions before the merge (although of course bug fixes can go in later ;-). Peter, The patches that touch ARM and that could do with maintainer sign-off are: tcg: enable MTTCG by default for ARM on x86 hosts target-arm: ensure all cross vCPUs TLB flushes complete target-arm: introduce ARM_CP_EXIT_PC target-arm/cpu.h: make ARM_CP defined consistent target-arm: don't generate WFE/YIELD calls for MTTCG target-arm/powerctl: defer cpu reset work to CPU context cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap tcg: drop global lock during TCG code execution Cheers, Alex Bennée (19): docs: new design document multi-thread-tcg.txt tcg: move TCG_MO/BAR types into own file tcg: add kick timer for single-threaded vCPU emulation tcg: rename tcg_current_cpu to tcg_current_rr_cpu tcg: remove global exit_request tcg: enable tb_lock() for SoftMMU tcg: enable thread-per-vCPU cputlb: add assert_cpu_is_self checks cputlb: tweak qemu_ram_addr_from_host_nofail reporting cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap cputlb: add tlb_flush_by_mmuidx async routines cputlb: atomically update tlb fields used by tlb_reset_dirty cputlb: introduce tlb_flush_*_all_cpus[_synced] target-arm/powerctl: defer cpu reset work to CPU context target-arm: don't generate WFE/YIELD calls for MTTCG target-arm/cpu.h: make ARM_CP defined consistent target-arm: introduce ARM_CP_EXIT_PC target-arm: ensure all cross vCPUs TLB flushes complete tcg: enable MTTCG by default for ARM on x86 hosts Jan Kiszka (1): tcg: drop global lock during TCG code execution KONRAD Frederic (2): tcg: add options for enabling MTTCG cputlb: introduce tlb_flush_* async work. Pranith Kumar (3): mttcg: translate-all: Enable locking debug in a debug build mttcg: Add missing tb_lock/unlock() in cpu_exec_step() tcg: handle EXCP_ATOMIC exception for system emulation configure | 6 + cpu-exec-common.c | 3 - cpu-exec.c | 41 ++-- cpus.c | 343 ++++++++++++++++++++++++++------- cputlb.c | 465 +++++++++++++++++++++++++++++++++++++-------- docs/multi-thread-tcg.txt | 350 ++++++++++++++++++++++++++++++++++ exec.c | 12 +- hw/core/irq.c | 1 + hw/i386/kvmvapic.c | 4 +- hw/intc/arm_gicv3_cpuif.c | 3 + hw/ppc/ppc.c | 16 +- hw/ppc/spapr.c | 3 + include/exec/cputlb.h | 2 - include/exec/exec-all.h | 130 +++++++++++-- include/qom/cpu.h | 16 ++ include/sysemu/cpus.h | 2 + memory.c | 2 + qemu-options.hx | 20 ++ qom/cpu.c | 10 + target/arm/arm-powerctl.c | 146 ++++++++------ target/arm/cpu.h | 32 ++-- target/arm/helper.c | 275 ++++++++++++++------------- target/arm/op_helper.c | 50 ++++- target/arm/translate-a64.c | 12 +- target/arm/translate.c | 24 ++- target/i386/smm_helper.c | 7 + target/s390x/misc_helper.c | 5 +- target/sparc/ldst_helper.c | 8 +- tcg/i386/tcg-target.h | 11 ++ tcg/tcg-mo.h | 48 +++++ tcg/tcg.h | 27 +-- translate-all.c | 66 ++----- translate-common.c | 21 +- vl.c | 49 ++++- 34 files changed, 1731 insertions(+), 479 deletions(-) create mode 100644 docs/multi-thread-tcg.txt create mode 100644 tcg/tcg-mo.h -- 2.11.0