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Iglesias" , Alistair Francis , Peter Maydell , Jason Wang , Markus Armbruster , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?b?ZMOp?= , Tong Ho , Ramon Fried Subject: [PATCH v3 00/11] Cadence GEM Fixes Date: Fri, 8 May 2020 16:30:34 +0530 Message-Id: <1588935645-20351-1-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFTY:; SFS:(396003)(136003)(39860400002)(376002)(346002)(46966005)(33430700001)(42186006)(356005)(5660300002)(82310400002)(47076004)(336012)(8676002)(426003)(2616005)(4326008)(6266002)(70586007)(110136005)(82740400003)(33440700001)(186003)(478600001)(8936002)(316002)(81166007)(2906002)(70206006)(6666004)(26005)(36756003)(42866002); DIR:OUT; SFP:1101; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5a920c2e-3936-4178-f411-08d7f3402c84 X-MS-TrafficTypeDiagnostic: SN1PR02MB3728: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4502; X-Forefront-PRVS: 039735BC4E X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7hgRnkaE0af4ufMQ8W1s7RIBcLQUGMPGvXZzIbjWtYu1LBsVzM8DZmJW+rBzcfhpRw/yawyiL0NU47/auEkO5a+/3RC5eNDY9+tpNTV8AmXINw/51+Ncj9V18Sv+O0ubObK+Yflfo8flzBdwnkvbnBc+iJrnDhvUjdtT0bQB8j+AryVCb+UwrBDOFIsL62j94OwrUx+uzGclI6Ut4IfN0Qi9s12e0/Wy8ftpiC9jjy6EnIcoy84n+tHB2fbJrHRRFSxV2+klpLZ2OFf/Kx3LAQc8JCOQEZXhZAyovMy2WzFepFIqIiko9nl7i41XeQA2r61NPxzstIeEJuxIt7CkB1m3WdTZ6UKwVcqwmVSzzX6zLlB9pCo+exYBVT8NBRO6SRADT2hi+YK2pyD8IEqIiDNNM2OtgE+TdcR+m6S36kS7cZRMYnwh7+ZrDOFDYdAyLMc4i45LfgFrP4vya++N91hQ5yg+HM/1niCWMm6xBEwp3ccNad+AYKIqqylGQ/lih4G2Nw3qjKfdyBBBjYrD5e6TIKwBe12mCsTQx6sirR47SIr1S93S7AMG5Wt3SXMA+Dj8jRhuRW1BZkxOiPNfIv+NmdaAW8L1XbtCfNi0FQY= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 May 2020 11:08:44.6451 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a920c2e-3936-4178-f411-08d7f3402c84 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR02MB3728 Received-SPF: pass client-ip=40.107.93.85; envelope-from=saipava@xilinx.com; helo=NAM10-DM6-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/08 07:23:48 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, Following patch series fixes issues with priority queues, Adds JUMBO Frame support, Makes Debug statements compilable & Fixes related to multicast frames. Changes for V2: Fixed build failure on fedora docker machine Fix buggy debug print to use sized integer casting Changes for V3: 1/11: Fixed debug statments to use %u and %zd Remove rxoffset for buffer address 2/11: Add inline functions to get tx/rx queue base address. 4/11: fix read only mask 5/11: Move packet buffers to CadenceGEMState 6/11: Add JUMBO MAX LEN register Sai Pavan Boddu (10): net: cadence_gem: Fix debug statements net: cadence_gem: Fix the queue address update during wrap around net: cadence_gem: Fix irq update w.r.t queue net: cadence_gem: Define access permission for interrupt registers net: cadence_gem: Set ISR according to queue in use net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState net: cadence_gem: Add support for jumbo frames net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg net: cadence_gem: Update the reset value for interrupt mask register net: cadence_gem: TX_LAST bit should be set by guest Tong Ho (1): net: cadence_gem: Fix RX address filtering hw/net/cadence_gem.c | 236 ++++++++++++++++++++++++++----------------- include/hw/net/cadence_gem.h | 3 + 2 files changed, 145 insertions(+), 94 deletions(-)