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[46.33.159.2]) by mx.google.com with ESMTPSA id v6sm6823630wiy.11.2013.05.07.19.35.12 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 07 May 2013 19:35:13 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: Stefano.Stabellini@eu.citrix.com, patches@linaro.org, ian.campbell@citrix.com, Julien Grall Subject: [PATCH V2 33/33] xen/arm64: Remove hardcoded value for gic in assembly code Date: Wed, 8 May 2013 03:33:53 +0100 Message-Id: <41669abc39764ea111d424ba7bff01e0da0300dd.1367979526.git.julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQnoK8plUlFlE5IiMKHO54qQvuJbFEorJGpUayjYJz5BRi97A/zsqMr11qVqw1SH3lNhpiHo X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , - arm64: use V2M_GIC_BASE_ADDRESS - only expose GIC_*_ADDRESS to assembly. The C code uses base addresses provide by the device tree Signed-off-by: Julien Grall Acked-by: Ian Campbell Changes in v2: - Remove stray gi"t diff" --- xen/arch/arm/arm64/mode_switch.S | 7 ++++--- xen/include/asm-arm/config.h | 8 ++++++-- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/arm64/mode_switch.S b/xen/arch/arm/arm64/mode_switch.S index 4c38181..d115706 100644 --- a/xen/arch/arm/arm64/mode_switch.S +++ b/xen/arch/arm/arm64/mode_switch.S @@ -21,6 +21,7 @@ #include #include #include +#include /* Get up a CPU into EL2. Clobbers x0-x3. * @@ -53,18 +54,18 @@ enter_el2_mode: */ cbnz x22, 1f - ldr x1, =(GIC_BASE_ADDRESS+GIC_DR_OFFSET) // GICD_CTLR + ldr x1, =(V2M_GIC_BASE_ADDRESS+GIC_DR_OFFSET) // GICD_CTLR mov w0, #3 // EnableGrp0 | EnableGrp1 str w0, [x1] -1: ldr x1, =(GIC_BASE_ADDRESS+GIC_DR_OFFSET+0x80) // GICD_IGROUPR +1: ldr x1, =(V2M_GIC_BASE_ADDRESS+GIC_DR_OFFSET+0x80) // GICD_IGROUPR mov w0, #~0 // Grp1 interrupts str w0, [x1], #4 b.ne 2f // Only local interrupts for secondary CPUs str w0, [x1], #4 str w0, [x1], #4 -2: ldr x1, =(GIC_BASE_ADDRESS+GIC_CR_OFFSET) // GICC_CTLR +2: ldr x1, =(V2M_GIC_BASE_ADDRESS+GIC_CR_OFFSET) // GICC_CTLR ldr w0, [x1] mov w0, #3 // EnableGrp0 | EnableGrp1 str w0, [x1] diff --git a/xen/include/asm-arm/config.h b/xen/include/asm-arm/config.h index 6414c89..e3cfaf1 100644 --- a/xen/include/asm-arm/config.h +++ b/xen/include/asm-arm/config.h @@ -141,12 +141,16 @@ extern unsigned long frametable_virt_end; #define watchdog_disable() ((void)0) #define watchdog_enable() ((void)0) -/* Board-specific: base address of GIC + its regs */ -#define GIC_BASE_ADDRESS 0x2c000000 +#ifdef __ASSEMBLY__ +/* Board-specific: regs base address for the GIC + * Theses constants are only intend to be used in assembly file + * because the DT is not yet parsed. + */ #define GIC_DR_OFFSET 0x1000 #define GIC_CR_OFFSET 0x2000 #define GIC_HR_OFFSET 0x4000 /* Guess work http://lists.infradead.org/pipermail/linux-arm-kernel/2011-September/064219.html */ #define GIC_VR_OFFSET 0x6000 /* Virtual Machine CPU interface) */ +#endif /* __ASSEMBLY__ */ #endif /* __ARM_CONFIG_H__ */ /*