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[216.34.181.88]) by mx.google.com with ESMTPS id h16si2268541ioh.103.2015.05.29.05.34.05 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 29 May 2015 05:34:06 -0700 (PDT) Received-SPF: pass (google.com: domain of edk2-devel-bounces@lists.sourceforge.net designates 216.34.181.88 as permitted sender) client-ip=216.34.181.88; Received: from localhost ([127.0.0.1] helo=sfs-ml-3.v29.ch3.sourceforge.com) by sfs-ml-3.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1YyJU2-00039L-2z; Fri, 29 May 2015 12:33:54 +0000 Received: from sog-mx-4.v43.ch3.sourceforge.com ([172.29.43.194] helo=mx.sourceforge.net) by sfs-ml-3.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1YyJU1-00039G-47 for edk2-devel@lists.sourceforge.net; Fri, 29 May 2015 12:33:53 +0000 Received-SPF: pass (sog-mx-4.v43.ch3.sourceforge.com: domain of linaro.org designates 209.85.212.169 as permitted sender) client-ip=209.85.212.169; envelope-from=ard.biesheuvel@linaro.org; helo=mail-wi0-f169.google.com; Received: from mail-wi0-f169.google.com ([209.85.212.169]) by sog-mx-4.v43.ch3.sourceforge.com with esmtps (TLSv1:RC4-SHA:128) (Exim 4.76) id 1YyJU0-00077F-7b for edk2-devel@lists.sourceforge.net; Fri, 29 May 2015 12:33:53 +0000 Received: by wicmx19 with SMTP id mx19so14775554wic.0 for ; Fri, 29 May 2015 05:33:46 -0700 (PDT) X-Received: by 10.194.71.226 with SMTP id y2mr148154wju.34.1432902826180; Fri, 29 May 2015 05:33:46 -0700 (PDT) Received: from localhost.localdomain ([109.112.79.182]) by mx.google.com with ESMTPSA id ex5sm2953226wib.2.2015.05.29.05.33.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 May 2015 05:33:45 -0700 (PDT) From: Ard Biesheuvel To: lersek@redhat.com, olivier.martin@arm.com, leif.lindholm@linaro.org, edk2-devel@lists.sourceforge.net Date: Fri, 29 May 2015 14:33:34 +0200 Message-Id: <1432902820-18721-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432902820-18721-1-git-send-email-ard.biesheuvel@linaro.org> References: <1432902820-18721-1-git-send-email-ard.biesheuvel@linaro.org> X-Spam-Score: -1.5 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record X-Headers-End: 1YyJU0-00077F-7b Subject: [edk2] [PATCH 1/7] ArmPkg: reduce sysreg access count in GIC revision probe X-BeenThere: edk2-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list Reply-To: edk2-devel@lists.sourceforge.net List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.sourceforge.net X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Accesses to system registers are disproportionately heavy-weight when executed under virtualization, since each one involves two world switches (from guest to host and back again). So change the sequence that enables the GIC SRE interface so that it performs only a single sysreg read to test whether the SRE interface is enabled already, and only performs a write and an additional read if that turns out not to be the case. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c | 10 ++++++++-- ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c | 10 ++++++++-- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c b/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c index 9da69b2131e3..88fa4621e613 100644 --- a/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c +++ b/ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c @@ -23,6 +23,8 @@ ArmGicGetSupportedArchRevision ( VOID ) { + UINT32 IccSre; + // Ideally we would like to use the GICC IIDR Architecture version here, but // this does not seem to be very reliable as the implementation could easily // get it wrong. It is more reliable to check if the GICv3 System Register @@ -37,8 +39,12 @@ ArmGicGetSupportedArchRevision ( // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started // at the same exception level. // It is the OS responsibility to set this bit. - ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE); - if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) { + IccSre = ArmGicV3GetControlSystemRegisterEnable (); + if (!(IccSre & ICC_SRE_EL2_SRE)) { + ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE); + IccSre = ArmGicV3GetControlSystemRegisterEnable (); + } + if (IccSre & ICC_SRE_EL2_SRE) { return ARM_GIC_ARCH_REVISION_3; } } diff --git a/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c b/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c index f360a405833d..9ef56efeaa7b 100644 --- a/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c +++ b/ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c @@ -23,6 +23,8 @@ ArmGicGetSupportedArchRevision ( VOID ) { + UINT32 IccSre; + // Ideally we would like to use the GICC IIDR Architecture version here, but // this does not seem to be very reliable as the implementation could easily // get it wrong. It is more reliable to check if the GICv3 System Register @@ -37,8 +39,12 @@ ArmGicGetSupportedArchRevision ( // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started // at the same exception level. // It is the OS responsibility to set this bit. - ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE); - if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) { + IccSre = ArmGicV3GetControlSystemRegisterEnable (); + if (!(IccSre & ICC_SRE_EL2_SRE)) { + ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE); + IccSre = ArmGicV3GetControlSystemRegisterEnable (); + } + if (IccSre & ICC_SRE_EL2_SRE) { return ARM_GIC_ARCH_REVISION_3; } }