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[50.57.142.19]) by mx.google.com with ESMTPS id y195si4146201qky.81.2015.05.17.13.06.34 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 17 May 2015 13:06:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Yu4nv-0001SW-DK; Sun, 17 May 2015 20:04:55 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Yu4nt-0001QH-O7 for xen-devel@lists.xen.org; Sun, 17 May 2015 20:04:53 +0000 Received: from [193.109.254.147] by server-10.bemta-14.messagelabs.com id F6/B5-02785-464F8555; Sun, 17 May 2015 20:04:52 +0000 X-Env-Sender: parth.dixit@linaro.org X-Msg-Ref: server-6.tower-27.messagelabs.com!1431893090!18238003!1 X-Originating-IP: [209.85.220.53] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 6.13.15; banners=-,-,- X-VirusChecked: Checked Received: (qmail 21321 invoked from network); 17 May 2015 20:04:51 -0000 Received: from mail-pa0-f53.google.com (HELO mail-pa0-f53.google.com) (209.85.220.53) by server-6.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 17 May 2015 20:04:51 -0000 Received: by pacwv17 with SMTP id wv17so119732394pac.2 for ; Sun, 17 May 2015 13:04:49 -0700 (PDT) X-Received: by 10.70.134.35 with SMTP id ph3mr37394203pdb.91.1431893089864; Sun, 17 May 2015 13:04:49 -0700 (PDT) Received: from localhost.localdomain ([117.247.24.139]) by mx.google.com with ESMTPSA id j9sm7838401pdm.53.2015.05.17.13.04.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 May 2015 13:04:49 -0700 (PDT) From: Parth Dixit To: xen-devel@lists.xen.org Date: Mon, 18 May 2015 01:33:34 +0530 Message-Id: <1431893048-5214-8-git-send-email-parth.dixit@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431893048-5214-1-git-send-email-parth.dixit@linaro.org> References: <1431893048-5214-1-git-send-email-parth.dixit@linaro.org> Cc: keir@xen.org, ian.campbell@citrix.com, andrew.cooper3@citrix.com, tim@xen.org, julien.grall@citrix.com, stefano.stabellini@citrix.com, jbeulich@suse.com, parth.dixit@linaro.org, christoffer.dall@linaro.org Subject: [Xen-devel] [PATCH v2 07/41] arm/acpi : Introduce ARM Boot Architecture Flags in FADT X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: parth.dixit@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: The Power State Coordination Interface (PSCI) defines an API that can be used to coordinate power control amongst the various supervisory systems concurrently running on a device. ACPI support for this technology would require the addition of two flags: PSCI_COMPLIANT and PSCI_USE_HVC. When set, the former signals to the OS that the hardware is PSCI compliant. The latter selects the appropriate conduit for PSCI calls by toggling between Hypervisor Calls (HVC) and Secure Monitor Calls (SMC). An ARM Boot Architecture Flags structure to support new ARM hardware was introduced in FADT in ACPI 5.1, add the code accordingly to implement that in ACPICA core. Since ACPI 5.1 doesn't support self defined PSCI function IDs, which means that only PSCI 0.2+ is supported in ACPI. Signed-off-by: Hanjun Guo Signed-off-by: Naresh Bhat --- xen/include/acpi/actbl.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/xen/include/acpi/actbl.h b/xen/include/acpi/actbl.h index 856945d..96fd1d8 100644 --- a/xen/include/acpi/actbl.h +++ b/xen/include/acpi/actbl.h @@ -244,7 +244,8 @@ struct acpi_table_fadt { u32 flags; /* Miscellaneous flag bits (see below for individual flags) */ struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */ u8 reset_value; /* Value to write to the reset_register port to reset the system */ - u8 reserved4[3]; /* Reserved, must be zero */ + u16 arm_boot_flags; /* ARM Boot Architecture Flags (see below for individual flags) */ + u8 minor_revision; /* Minor version of this FADT structure */ u64 Xfacs; /* 64-bit physical address of FACS */ u64 Xdsdt; /* 64-bit physical address of DSDT */ struct acpi_generic_address xpm1a_event_block; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */ @@ -270,6 +271,11 @@ struct acpi_table_fadt { #define FADT2_REVISION_ID 3 +/* Masks for FADT ARM Boot Architecture Flags (arm_boot_flags) */ + +#define ACPI_FADT_PSCI_COMPLIANT (1) /* 00: PSCI 0.2+ is implemented */ +#define ACPI_FADT_PSCI_USE_HVC (1<<1) /* 01: HVC must be used instead of SMC as the PSCI conduit */ + /* Masks for FADT flags */ #define ACPI_FADT_WBINVD (1) /* 00: [V1] The wbinvd instruction works properly */ @@ -345,7 +351,7 @@ enum acpi_prefered_pm_profiles { * FADT V5 size: 0x10C */ #define ACPI_FADT_V1_SIZE (u32) (ACPI_FADT_OFFSET (flags) + 4) -#define ACPI_FADT_V2_SIZE (u32) (ACPI_FADT_OFFSET (reserved4[0]) + 3) +#define ACPI_FADT_V2_SIZE (u32) (ACPI_FADT_OFFSET (arm_boot_flags) + 3) #define ACPI_FADT_V3_SIZE (u32) (ACPI_FADT_OFFSET (sleep_control)) #define ACPI_FADT_V5_SIZE (u32) (sizeof (struct acpi_table_fadt))