From patchwork Thu Feb 12 07:22:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier Martin X-Patchwork-Id: 44594 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f199.google.com (mail-wi0-f199.google.com [209.85.212.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 72F562151D for ; Thu, 12 Feb 2015 07:22:51 +0000 (UTC) Received: by mail-wi0-f199.google.com with SMTP id bs8sf1202300wib.2 for ; Wed, 11 Feb 2015 23:22:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:subject:precedence:reply-to:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :content-type:content-transfer-encoding:errors-to:x-original-sender :x-original-authentication-results:mailing-list; bh=6nvT6u50n+FRfFq3YHPJMgTUINvifvluGN8YEmapROI=; b=dIXWF+EXBd0Mz9M4Jx9MM3WoSHQDKT207MXUOErPQE0mNWb/ef82HQslMVo8VM+AeJ a9Lc8O3prn9aMF+74E809xMyONS/RXU6G6qoAeRvNOPLmwYC/Tx2cs9Gv18Oc+9yCVjH rU2WDhMTIiqrgMBrGStUAjCjS4xKZknOwNSgDCHJHngV0mCOnqFZhnWQ4afQAqlE41+t bm9+KEYfSjB8x9I78uht5/qdFtNnCXHQlYQrbgz7V8ickapzDOutOfCKgn0PZYn5x9z4 wthue+6R3FEvmn+r8Ir4YKgMQRi4GnCVoo82fG/AWB4ACwkWMZr24b49f2ckh0XaQrwi BGFg== X-Gm-Message-State: ALoCoQnJk9vPOk8g1EL/BUWscHQ1yesBV9gQuOi5Ym2LYOWBSFhYo4vo533mwCZjIEu5ORBLsJ9K X-Received: by 10.194.201.10 with SMTP id jw10mr316195wjc.3.1423725770754; Wed, 11 Feb 2015 23:22:50 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.204.12 with SMTP id ku12ls29730lac.105.gmail; Wed, 11 Feb 2015 23:22:50 -0800 (PST) X-Received: by 10.152.181.129 with SMTP id dw1mr1918889lac.101.1423725770588; Wed, 11 Feb 2015 23:22:50 -0800 (PST) Received: from mail-la0-f43.google.com (mail-la0-f43.google.com. [209.85.215.43]) by mx.google.com with ESMTPS id ww5si2352277lbb.22.2015.02.11.23.22.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Feb 2015 23:22:50 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) client-ip=209.85.215.43; Received: by labgd6 with SMTP id gd6so8254960lab.7 for ; Wed, 11 Feb 2015 23:22:50 -0800 (PST) X-Received: by 10.152.181.168 with SMTP id dx8mr1978338lac.76.1423725770489; Wed, 11 Feb 2015 23:22:50 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.35.133 with SMTP id h5csp272815lbj; Wed, 11 Feb 2015 23:22:49 -0800 (PST) X-Received: by 10.43.34.137 with SMTP id ss9mr7219541icb.11.1423725766411; Wed, 11 Feb 2015 23:22:46 -0800 (PST) Received: from lists.sourceforge.net (lists.sourceforge.net. [216.34.181.88]) by mx.google.com with ESMTPS id o141si2445552ioe.39.2015.02.11.23.22.45 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 11 Feb 2015 23:22:46 -0800 (PST) Received-SPF: pass (google.com: domain of edk2-devel-bounces@lists.sourceforge.net designates 216.34.181.88 as permitted sender) client-ip=216.34.181.88; Received: from localhost ([127.0.0.1] helo=sfs-ml-2.v29.ch3.sourceforge.com) by sfs-ml-2.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1YLo6f-0001fS-VT; Thu, 12 Feb 2015 07:22:37 +0000 Received: from sog-mx-2.v43.ch3.sourceforge.com ([172.29.43.192] helo=mx.sourceforge.net) by sfs-ml-2.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1YLo6e-0001f9-PM for edk2-devel@lists.sourceforge.net; Thu, 12 Feb 2015 07:22:36 +0000 Received-SPF: pass (sog-mx-2.v43.ch3.sourceforge.com: domain of arm.com designates 195.130.217.12 as permitted sender) client-ip=195.130.217.12; envelope-from=olivier.martin@arm.com; helo=service88.mimecast.com; Received: from service88.mimecast.com ([195.130.217.12]) by sog-mx-2.v43.ch3.sourceforge.com with esmtp (Exim 4.76) id 1YLo6d-0006R7-QU for edk2-devel@lists.sourceforge.net; Thu, 12 Feb 2015 07:22:36 +0000 Received: from emea-cam-gw1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (Using TLS) by service88.mimecast.com; Thu, 12 Feb 2015 07:22:29 +0000 Received: from EMEA-CAM-GW3.Emea.Arm.com (10.1.106.86) by emea-cam-gw1.Emea.Arm.com (10.1.248.204) with Microsoft SMTP Server (TLS) id 8.3.298.1; Thu, 12 Feb 2015 07:22:28 +0000 Received: from e102023-loan.cambridge.arm.com (10.1.2.79) by EMEA-CAM-GW3.Emea.Arm.com (10.1.106.85) with Microsoft SMTP Server id 8.3.298.1; Thu, 12 Feb 2015 07:22:27 +0000 From: Olivier Martin To: Date: Thu, 12 Feb 2015 07:22:10 +0000 Message-ID: <1423725731-31430-6-git-send-email-olivier.martin@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1423725731-31430-1-git-send-email-olivier.martin@arm.com> References: <1423725731-31430-1-git-send-email-olivier.martin@arm.com> MIME-Version: 1.0 X-MC-Unique: 115021207222900402 X-Spam-Score: -1.5 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record -0.0 AWL AWL: Adjusted score from AWL reputation of From: address X-Headers-End: 1YLo6d-0006R7-QU Subject: [edk2] [PATCH 5/6] ArmPkg: enable ARE bit before driving GICv3 in native mode X-BeenThere: edk2-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list Reply-To: edk2-devel@lists.sourceforge.net List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: edk2-devel-bounces@lists.sourceforge.net X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: olivier.martin@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Ard Biesheuvel The GICv3 driver must use native mode to drive a GICv3 due to the fact that v2 compatibility is optional in the v3 spec. However, if v2 compatibility is implemented, it is the default and needs to be disabled first by setting the Affinity Routing Enable (ARE) bit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-By: Olivier Martin Signed-off-by: Olivier Martin --- ArmPkg/ArmPkg.dec | 3 +++ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf | 3 ++- ArmPkg/Drivers/ArmGic/ArmGicLib.c | 6 +++--- ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 3 +++ ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf | 3 +++ ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 8 ++++++++ ArmPkg/Include/Library/ArmGicLib.h | 3 +++ 7 files changed, 25 insertions(+), 4 deletions(-) -- 1.9.1 -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 ------------------------------------------------------------------------------ Dive into the World of Parallel Programming. The Go Parallel Website, sponsored by Intel and developed in partnership with Slashdot Media, is your hub for all things parallel software development, from weekly thought leadership blogs to news, videos, case studies, tutorials and more. Take a look and join the conversation now. http://goparallel.sourceforge.net/ diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 75960ed..ced3929 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -69,6 +69,9 @@ # Linux (instead of PSCI) gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033 + # Define if the GICv3 controller should use the GICv2 legacy + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 + [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006 diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf index 92f3b1d..e554301 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf @@ -1,7 +1,7 @@ #/** @file # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2012 - 2015, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -54,6 +54,7 @@ gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicRedistributorsBase gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy [Depex] gEfiCpuArchProtocolGuid diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c index 7c53e39..48708e3 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -186,7 +186,7 @@ ArmGicEnableInterrupt ( RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); - if (Revision == ARM_GIC_ARCH_REVISION_2) { + if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { // Write set-enable register MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift); } else { @@ -219,7 +219,7 @@ ArmGicDisableInterrupt ( RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); - if (Revision == ARM_GIC_ARCH_REVISION_2) { + if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { // Write clear-enable register MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift); } else { @@ -252,7 +252,7 @@ ArmGicIsInterruptEnabled ( RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); - if (Revision == ARM_GIC_ARCH_REVISION_2) { + if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0); } else { GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision); diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf index 9f46679..2ae3fd3 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf @@ -47,3 +47,6 @@ [Pcd] gArmPlatformTokenSpaceGuid.PcdCoreCount + +[FeaturePcd] + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf index 9097b37..7d4e49e 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf @@ -48,3 +48,6 @@ [Pcd] gArmPlatformTokenSpaceGuid.PcdCoreCount + +[FeaturePcd] + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index e94e015..f3bf191 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -249,6 +249,14 @@ GicV3DxeInitialize ( mGicRedistributorsBase = PcdGet32 (PcdGicRedistributorsBase); mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase); + // + // We will be driving this GIC in native v3 mode, i.e., with Affinity + // Routing enabled. So ensure that the ARE bit is set. + // + if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { + MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE); + } + for (Index = 0; Index < mGicNumInterrupts; Index++) { GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index); diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h index 2ab9977..e2a4818 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -53,6 +53,9 @@ typedef enum { // GICv3 specific registers #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers +// the Affinity Routing Enable (ARE) bit in GICD_CTLR +#define ARM_GIC_ICDDCR_ARE (1 << 4) + // // GIC Redistributor //