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[50.57.142.19]) by mx.google.com with ESMTPS id l9si2083060qaf.70.2015.02.04.06.04.53 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 04 Feb 2015 06:04:53 -0800 (PST) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YJ0Yn-0006rv-O3; Wed, 04 Feb 2015 14:04:05 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YJ0Ym-0006r2-RM for xen-devel@lists.xen.org; Wed, 04 Feb 2015 14:04:04 +0000 Received: from [85.158.139.211] by server-16.bemta-5.messagelabs.com id 81/D0-02804-4D622D45; Wed, 04 Feb 2015 14:04:04 +0000 X-Env-Sender: parth.dixit@linaro.org X-Msg-Ref: server-15.tower-206.messagelabs.com!1423058642!7770341!1 X-Originating-IP: [209.85.220.48] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.13.4; banners=-,-,- X-VirusChecked: Checked Received: (qmail 7056 invoked from network); 4 Feb 2015 14:04:03 -0000 Received: from mail-pa0-f48.google.com (HELO mail-pa0-f48.google.com) (209.85.220.48) by server-15.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 4 Feb 2015 14:04:03 -0000 Received: by mail-pa0-f48.google.com with SMTP id ey11so2954839pad.7 for ; Wed, 04 Feb 2015 06:04:01 -0800 (PST) X-Received: by 10.70.132.39 with SMTP id or7mr5280648pdb.90.1423058641845; Wed, 04 Feb 2015 06:04:01 -0800 (PST) Received: from parthd-ubunutu.qualcomm.com ([202.46.23.62]) by mx.google.com with ESMTPSA id kg12sm2161881pbb.44.2015.02.04.06.03.57 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Feb 2015 06:04:00 -0800 (PST) From: parth.dixit@linaro.org To: xen-devel@lists.xen.org Date: Wed, 4 Feb 2015 19:31:54 +0530 Message-Id: <1423058539-26403-11-git-send-email-parth.dixit@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1423058539-26403-1-git-send-email-parth.dixit@linaro.org> References: <1423058539-26403-1-git-send-email-parth.dixit@linaro.org> Cc: ian.campbell@citrix.com, Naresh Bhat , julien.grall@linaro.org, tim@xen.org, stefano.stabellini@citrix.com, jbeulich@suse.com, christoffer.dall@linaro.org Subject: [Xen-devel] [PATCH RFC 10/35] asm / arm: Introduce cputype.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: parth.dixit@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: From: Naresh Bhat Introduce cputype.h file for arm Signed-off-by: Naresh Bhat --- xen/include/asm-arm/cputype.h | 83 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 xen/include/asm-arm/cputype.h diff --git a/xen/include/asm-arm/cputype.h b/xen/include/asm-arm/cputype.h new file mode 100644 index 0000000..0b454cc --- /dev/null +++ b/xen/include/asm-arm/cputype.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2012 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __ASM_CPUTYPE_H +#define __ASM_CPUTYPE_H + +#include + +#define INVALID_HWID ULONG_MAX + +#define MPIDR_HWID_BITMASK 0xff00ffffff + +#define MPIDR_LEVEL_BITS_SHIFT 3 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) + +#define MPIDR_LEVEL_SHIFT(level) \ + (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) + +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) + +#define read_cpuid(reg) ({ \ + u64 __val; \ + asm("mrs %0, " #reg : "=r" (__val)); \ + __val; \ +}) + +#define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_IMP_APM 0x50 + +#define ARM_CPU_PART_AEM_V8 0xD0F0 +#define ARM_CPU_PART_FOUNDATION 0xD000 +#define ARM_CPU_PART_CORTEX_A57 0xD070 + +#define APM_CPU_PART_POTENZA 0x0000 + +#ifndef __ASSEMBLY__ + +/* + * The CPU ID never changes at run time, so we might as well tell the + * compiler that it's constant. Use this function to read the CPU ID + * rather than directly reading processor_id or read_cpuid() directly. + */ +static inline u32 __attribute_const__ read_cpuid_id(void) +{ + return read_cpuid(MIDR_EL1); +} + +static inline u64 __attribute_const__ read_cpuid_mpidr(void) +{ + return read_cpuid(MPIDR_EL1); +} + +static inline unsigned int __attribute_const__ read_cpuid_implementor(void) +{ + return (read_cpuid_id() & 0xFF000000) >> 24; +} + +static inline unsigned int __attribute_const__ read_cpuid_part_number(void) +{ + return (read_cpuid_id() & 0xFFF0); +} + +static inline u32 __attribute_const__ read_cpuid_cachetype(void) +{ + return read_cpuid(CTR_EL0); +} + +#endif /* __ASSEMBLY__ */ + +#endif