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[50.57.142.19]) by mx.google.com with ESMTPS id l1si797256vcx.28.2014.11.19.07.30.04 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 19 Nov 2014 07:30:06 -0800 (PST) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Xr7BH-00006q-6o; Wed, 19 Nov 2014 15:28:31 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Xr7BF-00006Z-PB for xen-devel@lists.xen.org; Wed, 19 Nov 2014 15:28:29 +0000 Received: from [193.109.254.147] by server-1.bemta-14.messagelabs.com id 2B/62-02559-D17BC645; Wed, 19 Nov 2014 15:28:29 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-4.tower-27.messagelabs.com!1416410905!13542396!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.12.4; banners=-,-,- X-VirusChecked: Checked Received: (qmail 7483 invoked from network); 19 Nov 2014 15:28:28 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-4.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 19 Nov 2014 15:28:28 -0000 X-IronPort-AV: E=Sophos;i="5.07,417,1413244800"; d="scan'208";a="194425628" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.3.181.6; Wed, 19 Nov 2014 10:28:22 -0500 Received: from drall.uk.xensource.com ([10.80.16.71]) by ukmail1.uk.xensource.com with smtp (Exim 4.69) (envelope-from ) id 1Xr7B7-00059a-1o; Wed, 19 Nov 2014 15:28:22 +0000 Received: by drall.uk.xensource.com (sSMTP sendmail emulation); Wed, 19 Nov 2014 15:28:20 +0000 From: Ian Campbell To: Date: Wed, 19 Nov 2014 15:28:15 +0000 Message-ID: <1416410895-20461-5-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1416410868.29243.39.camel@citrix.com> References: <1416410868.29243.39.camel@citrix.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: Ian Campbell , julien.grall@linaro.org, tim@xen.org, Clark Laughlin , stefano.stabellini@eu.citrix.com, Pranavkumar Sawargaonkar Subject: [Xen-devel] [PATCH v2 for-4.5 5/5] xen: arm: Support the other 4 PCI buses on Xgene X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Currently we only establish specific mappings for pcie0, which is used on the Mustang platform. However at least McDivitt uses pcie3. So wire up all the others, based on whether the corresponding DT node is marked as available. This results in no change for Mustang. Signed-off-by: Ian Campbell Reviewed-by: Julien Grall Acked-by: Pranavkumar Sawargaonkar --- v2: - Didn't constify dt node pointer -- dt_find_compatible_node needs a non-const - Print a message when ignoring an unknown bus - Log with dt node full anme instead of CFG space address. - Log at start of xgene_storm_pcie_specific_mapping instead of in the caller after the fact. --- xen/arch/arm/platforms/xgene-storm.c | 89 +++++++++++++++++++++++++++++----- 1 file changed, 76 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c index 8c27f24..0b3492d 100644 --- a/xen/arch/arm/platforms/xgene-storm.c +++ b/xen/arch/arm/platforms/xgene-storm.c @@ -78,35 +78,35 @@ static int map_one_spi(struct domain *d, const char *what, return ret; } -/* - * Xen does not currently support mapping MMIO regions and interrupt - * for bus child devices (referenced via the "ranges" and - * "interrupt-map" properties to domain 0). Instead for now map the - * necessary resources manually. - */ -static int xgene_storm_specific_mapping(struct domain *d) +/* Creates MMIO mappings base..end as well as 4 SPIs from the given base. */ +static int xgene_storm_pcie_specific_mapping(struct domain *d, + const struct dt_device_node *node, + paddr_t base, paddr_t end, + int base_spi) { int ret; + printk("Mapping additional regions for PCIe device %s\n", + dt_node_full_name(node)); + /* Map the PCIe bus resources */ - ret = map_one_mmio(d, "PCI MEMORY", paddr_to_pfn(0x0e000000000UL), - paddr_to_pfn(0x01000000000UL)); + ret = map_one_mmio(d, "PCI MEMORY", paddr_to_pfn(base), paddr_to_pfn(end)); if ( ret ) goto err; - ret = map_one_spi(d, "PCI#INTA", 0xc2, DT_IRQ_TYPE_LEVEL_HIGH); + ret = map_one_spi(d, "PCI#INTA", base_spi+0, DT_IRQ_TYPE_LEVEL_HIGH); if ( ret ) goto err; - ret = map_one_spi(d, "PCI#INTB", 0xc3, DT_IRQ_TYPE_LEVEL_HIGH); + ret = map_one_spi(d, "PCI#INTB", base_spi+1, DT_IRQ_TYPE_LEVEL_HIGH); if ( ret ) goto err; - ret = map_one_spi(d, "PCI#INTC", 0xc4, DT_IRQ_TYPE_LEVEL_HIGH); + ret = map_one_spi(d, "PCI#INTC", base_spi+2, DT_IRQ_TYPE_LEVEL_HIGH); if ( ret ) goto err; - ret = map_one_spi(d, "PCI#INTD", 0xc5, DT_IRQ_TYPE_LEVEL_HIGH); + ret = map_one_spi(d, "PCI#INTD", base_spi+3, DT_IRQ_TYPE_LEVEL_HIGH); if ( ret ) goto err; @@ -115,6 +115,69 @@ err: return ret; } +/* + * Xen does not currently support mapping MMIO regions and interrupt + * for bus child devices (referenced via the "ranges" and + * "interrupt-map" properties to domain 0). Instead for now map the + * necessary resources manually. + */ +static int xgene_storm_specific_mapping(struct domain *d) +{ + struct dt_device_node *node = NULL; + int ret; + + while ( (node = dt_find_compatible_node(node, "pci", "apm,xgene-pcie")) ) + { + u64 addr; + + /* Identify the bus via it's control register address */ + ret = dt_device_get_address(node, 0, &addr, NULL); + if ( ret < 0 ) + return ret; + + if ( !dt_device_is_available(node) ) + continue; + + switch ( addr ) + { + case 0x1f2b0000: /* PCIe0 */ + ret = xgene_storm_pcie_specific_mapping(d, + node, + 0x0e000000000UL, 0x10000000000UL, 0xc2); + break; + case 0x1f2c0000: /* PCIe1 */ + ret = xgene_storm_pcie_specific_mapping(d, + node, + 0x0d000000000UL, 0x0e000000000UL, 0xc8); + break; + case 0x1f2d0000: /* PCIe2 */ + ret = xgene_storm_pcie_specific_mapping(d, + node, + 0x09000000000UL, 0x0a000000000UL, 0xce); + break; + case 0x1f500000: /* PCIe3 */ + ret = xgene_storm_pcie_specific_mapping(d, + node, + 0x0a000000000UL, 0x0c000000000UL, 0xd4); + break; + case 0x1f510000: /* PCIe4 */ + ret = xgene_storm_pcie_specific_mapping(d, + node, + 0x0c000000000UL, 0x0d000000000UL, 0xda); + break; + + default: + printk("Ignoring unknown PCI bus %s\n", dt_node_full_name(node)); + continue; + } + + if ( ret < 0 ) + return ret; + } + + return 0; +} + static void xgene_storm_reset(void) { void __iomem *addr;