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[50.57.142.19]) by mx.google.com with ESMTPS id t46si69429028qgt.120.2014.11.18.08.47.51 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 18 Nov 2014 08:47:52 -0800 (PST) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Xqluv-0007Nk-In; Tue, 18 Nov 2014 16:46:13 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Xqluu-0007ND-0r for xen-devel@lists.xen.org; Tue, 18 Nov 2014 16:46:12 +0000 Received: from [85.158.139.211] by server-16.bemta-5.messagelabs.com id C4/DA-29352-FC77B645; Tue, 18 Nov 2014 16:46:07 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-14.tower-206.messagelabs.com!1416329164!6654814!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.12.4; banners=-,-,- X-VirusChecked: Checked Received: (qmail 2406 invoked from network); 18 Nov 2014 16:46:06 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-14.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 18 Nov 2014 16:46:06 -0000 X-IronPort-AV: E=Sophos;i="5.07,410,1413244800"; d="scan'208";a="192549502" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.3.181.6; Tue, 18 Nov 2014 11:44:52 -0500 Received: from drall.uk.xensource.com ([10.80.16.71]) by ukmail1.uk.xensource.com with smtp (Exim 4.69) (envelope-from ) id 1Xqltb-0008T9-NM; Tue, 18 Nov 2014 16:44:52 +0000 Received: by drall.uk.xensource.com (sSMTP sendmail emulation); Tue, 18 Nov 2014 16:44:51 +0000 From: Ian Campbell To: Date: Tue, 18 Nov 2014 16:44:48 +0000 Message-ID: <1416329088-23328-4-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1416329045.17982.27.camel@citrix.com> References: <1416329045.17982.27.camel@citrix.com> MIME-Version: 1.0 X-DLP: MIA2 Cc: Ian Campbell , julien.grall@linaro.org, tim@xen.org, Clark Laughlin , stefano.stabellini@eu.citrix.com, Pranavkumar Sawargaonkar Subject: [Xen-devel] [PATCH for-4.5 4/4] xen: arm: Support the other 4 PCI buses on Xgene X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 74.125.83.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Currently we only establish specific mappings for pcie0, which is used on the Mustang platform. However at least McDivitt uses pcie3. So wire up all the others, based on whether the corresponding DT node is marked as available. This results in no change for Mustang. Signed-off-by: Ian Campbell --- xen/arch/arm/platforms/xgene-storm.c | 84 ++++++++++++++++++++++++++++------ 1 file changed, 71 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c index 6c432a1..926c325 100644 --- a/xen/arch/arm/platforms/xgene-storm.c +++ b/xen/arch/arm/platforms/xgene-storm.c @@ -78,35 +78,31 @@ static int map_one_spi(struct domain *d, const char *what, return ret; } -/* - * Xen does not currently support mapping MMIO regions and interrupt - * for bus child devices (referenced via the "ranges" and - * "interrupt-map" properties to domain 0). Instead for now map the - * necessary resources manually. - */ -static int xgene_storm_specific_mapping(struct domain *d) +/* Creates MMIO mappings base..end as well as 4 SPIs from the given base. */ +static int xgene_storm_pcie_specific_mapping(struct domain *d, + paddr_t base, paddr_t end, + int base_spi) { int ret; /* Map the PCIe bus resources */ - ret = map_one_mmio(d, "PCI MEMORY", paddr_to_pfn(0x0e000000000UL), - paddr_to_pfn(0x01000000000UL)); + ret = map_one_mmio(d, "PCI MEMORY", paddr_to_pfn(base), paddr_to_pfn(end)); if ( ret ) goto err; - ret = map_one_spi(d, "PCI#INTA", 0xc2, DT_IRQ_TYPE_LEVEL_HIGH); + ret = map_one_spi(d, "PCI#INTA", base_spi+0, DT_IRQ_TYPE_LEVEL_HIGH); if ( ret ) goto err; - ret = map_one_spi(d, "PCI#INTB", 0xc3, DT_IRQ_TYPE_LEVEL_HIGH); + ret = map_one_spi(d, "PCI#INTB", base_spi+1, DT_IRQ_TYPE_LEVEL_HIGH); if ( ret ) goto err; - ret = map_one_spi(d, "PCI#INTC", 0xc4, DT_IRQ_TYPE_LEVEL_HIGH); + ret = map_one_spi(d, "PCI#INTC", base_spi+2, DT_IRQ_TYPE_LEVEL_HIGH); if ( ret ) goto err; - ret = map_one_spi(d, "PCI#INTD", 0xc5, DT_IRQ_TYPE_LEVEL_HIGH); + ret = map_one_spi(d, "PCI#INTD", base_spi+3, DT_IRQ_TYPE_LEVEL_HIGH); if ( ret ) goto err; @@ -115,6 +111,68 @@ err: return ret; } +/* + * Xen does not currently support mapping MMIO regions and interrupt + * for bus child devices (referenced via the "ranges" and + * "interrupt-map" properties to domain 0). Instead for now map the + * necessary resources manually. + */ +static int xgene_storm_specific_mapping(struct domain *d) +{ + struct dt_device_node *node = NULL; + int ret; + + while ( (node = dt_find_compatible_node(node, "pci", "apm,xgene-pcie")) ) + { + u64 addr; + + /* Identify the bus via it's control register address */ + ret = dt_device_get_address(node, 0, &addr, NULL); + if ( ret < 0 ) + return ret; + + if ( !dt_device_is_available(node) ) + continue; + + switch ( addr ) + { + case 0x1f2b0000: /* PCIe0 */ + ret = xgene_storm_pcie_specific_mapping(d, + 0x0e000000000UL, 0x10000000000UL, 0xc2); + break; + case 0x1f2c0000: /* PCIe1 */ + ret = xgene_storm_pcie_specific_mapping(d, + 0x0d000000000UL, 0x0e000000000UL, 0xc8); + break; + case 0x1f2d0000: /* PCIe2 */ + ret = xgene_storm_pcie_specific_mapping(d, + 0x09000000000UL, 0x0a000000000UL, 0xce); + break; + case 0x1f500000: /* PCIe3 */ + ret = xgene_storm_pcie_specific_mapping(d, + 0x0a000000000UL, 0x0c000000000UL, 0xd4); + break; + case 0x1f510000: /* PCIe4 */ + ret = xgene_storm_pcie_specific_mapping(d, + 0x0c000000000UL, 0x0d000000000UL, 0xda); + break; + + default: + /* Ignore unknown PCI busses */ + ret = 0; + break; + } + + if ( ret < 0 ) + return ret; + + printk("Mapped additional regions for PCIe device at 0x%"PRIx64"\n", + addr); + } + + return 0; +} + static void xgene_storm_reset(void) { void __iomem *addr;