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[50.57.142.19]) by mx.google.com with ESMTPS id j7si10278700vcy.50.2014.11.03.08.49.20 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 03 Nov 2014 08:49:21 -0800 (PST) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XlKn6-0000Wo-Qf; Mon, 03 Nov 2014 16:47:40 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XlKn4-0000V5-Ge for xen-devel@lists.xen.org; Mon, 03 Nov 2014 16:47:38 +0000 Received: from [85.158.137.68] by server-11.bemta-3.messagelabs.com id 95/7A-25547-9A1B7545; Mon, 03 Nov 2014 16:47:37 +0000 X-Env-Sender: frediano.ziglio@huawei.com X-Msg-Ref: server-11.tower-31.messagelabs.com!1415033253!11360328!1 X-Originating-IP: [119.145.14.64] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTE5LjE0NS4xNC42NCA9PiA4MDE5MQ==\n X-StarScan-Received: X-StarScan-Version: 6.12.4; banners=-,-,- X-VirusChecked: Checked Received: (qmail 31763 invoked from network); 3 Nov 2014 16:47:36 -0000 Received: from szxga01-in.huawei.com (HELO szxga01-in.huawei.com) (119.145.14.64) by server-11.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 3 Nov 2014 16:47:36 -0000 Received: from 172.24.2.119 (EHLO szxeml424-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CDW69203; Tue, 04 Nov 2014 00:47:32 +0800 (CST) Received: from localhost.localdomain (10.47.77.41) by szxeml424-hub.china.huawei.com (10.82.67.163) with Microsoft SMTP Server id 14.3.158.1; Tue, 4 Nov 2014 00:47:24 +0800 From: Frediano Ziglio To: Ian Campbell , Stefano Stabellini , Tim Deegan , Julien Grall , Date: Mon, 3 Nov 2014 16:46:34 +0000 Message-ID: <1415033196-30529-6-git-send-email-frediano.ziglio@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415033196-30529-1-git-send-email-frediano.ziglio@huawei.com> References: <1415033196-30529-1-git-send-email-frediano.ziglio@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.77.41] X-CFilter-Loop: Reflected Cc: zoltan.kiss@huawei.com, xen-devel@lists.xen.org Subject: [Xen-devel] [PATCH v2 5/7] xen/arm: handle GICH register changes for hip04-d01 platform X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: frediano.ziglio@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: The GICH in this platform is mainly compatible with the standard GICv2 beside APR and LR register offsets. Signed-off-by: Frediano Ziglio --- xen/arch/arm/gic-v2.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 04e1850..411b104 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -61,6 +61,9 @@ #define GICH_V2_VMCR_PRIORITY_MASK 0x1f #define GICH_V2_VMCR_PRIORITY_SHIFT 27 +#define HIP04_GICH_APR 0x70 +#define HIP04_GICH_LR 0x80 + /* Global state */ static struct { paddr_t dbase; /* Address of distributor registers */ @@ -85,6 +88,8 @@ static DEFINE_PER_CPU(u16, gic_cpu_id); static unsigned int nr_gic_cpu_if = 8; static unsigned int gicd_sgi_target_shift = GICD_SGI_TARGET_SHIFT; static unsigned int gic_cpu_mask = 0xff; +static unsigned int gich_apr = GICH_APR; +static unsigned int gich_lr = GICH_LR; static inline void writeb_gicd(uint8_t val, unsigned int offset) { @@ -155,9 +160,9 @@ static void gicv2_save_state(struct vcpu *v) * accessed simultaneously by another pCPU. */ for ( i = 0; i < gicv2_info.nr_lrs; i++ ) - v->arch.gic.v2.lr[i] = readl_gich(GICH_LR + i * 4); + v->arch.gic.v2.lr[i] = readl_gich(gich_lr + i * 4); - v->arch.gic.v2.apr = readl_gich(GICH_APR); + v->arch.gic.v2.apr = readl_gich(gich_apr); v->arch.gic.v2.vmcr = readl_gich(GICH_VMCR); /* Disable until next VCPU scheduled */ writel_gich(0, GICH_HCR); @@ -168,9 +173,9 @@ static void gicv2_restore_state(const struct vcpu *v) int i; for ( i = 0; i < gicv2_info.nr_lrs; i++ ) - writel_gich(v->arch.gic.v2.lr[i], GICH_LR + i * 4); + writel_gich(v->arch.gic.v2.lr[i], gich_lr + i * 4); - writel_gich(v->arch.gic.v2.apr, GICH_APR); + writel_gich(v->arch.gic.v2.apr, gich_apr); writel_gich(v->arch.gic.v2.vmcr, GICH_VMCR); writel_gich(GICH_HCR_EN, GICH_HCR); } @@ -183,7 +188,7 @@ static void gicv2_dump_state(const struct vcpu *v) { for ( i = 0; i < gicv2_info.nr_lrs; i++ ) printk(" HW_LR[%d]=%x\n", i, - readl_gich(GICH_LR + i * 4)); + readl_gich(gich_lr + i * 4)); } else { @@ -437,12 +442,12 @@ static void gicv2_update_lr(int lr, const struct pending_irq *p, << GICH_V2_LR_PHYSICAL_SHIFT); } - writel_gich(lr_reg, GICH_LR + lr * 4); + writel_gich(lr_reg, gich_lr + lr * 4); } static void gicv2_clear_lr(int lr) { - writel_gich(0, GICH_LR + lr * 4); + writel_gich(0, gich_lr + lr * 4); } static int gicv2v_setup(struct domain *d) @@ -492,7 +497,7 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) { uint32_t lrv; - lrv = readl_gich(GICH_LR + lr * 4); + lrv = readl_gich(gich_lr + lr * 4); lr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) & GICH_V2_LR_PHYSICAL_MASK; lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; @@ -515,7 +520,7 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) << GICH_V2_LR_HW_SHIFT) | ((uint32_t)(lr_reg->grp & GICH_V2_LR_GRP_MASK) << GICH_V2_LR_GRP_SHIFT) ); - writel_gich(lrv, GICH_LR + lr * 4); + writel_gich(lrv, gich_lr + lr * 4); } static void gicv2_hcr_status(uint32_t flag, bool_t status) @@ -538,7 +543,7 @@ static unsigned int gicv2_read_vmcr_priority(void) static unsigned int gicv2_read_apr(int apr_reg) { - return readl_gich(GICH_APR); + return readl_gich(gich_apr); } static void gicv2_irq_enable(struct irq_desc *desc) @@ -727,6 +732,8 @@ static int __init gicv2_init_common(struct dt_device_node *node, const void *dat nr_gic_cpu_if = 16; gicd_sgi_target_shift = 8; gic_cpu_mask = 0xffff; + gich_apr = HIP04_GICH_APR; + gich_lr = HIP04_GICH_LR; } res = dt_device_get_address(node, 0, &gicv2.dbase, NULL);