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X-Original-Sender: frediano.ziglio@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: The GICH in this platform is mainly compatible with the standard GICv2 beside APR and LR register offsets. Signed-off-by: Frediano Ziglio --- xen/arch/arm/gic-v2.c | 24 ++++++++++++++---------- xen/include/asm-arm/gic.h | 2 ++ 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 85c7f11..e7bf331 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -84,6 +84,8 @@ static DEFINE_PER_CPU(u16, gic_cpu_id); /* Maximum cpu interface per GIC */ static unsigned int nr_gic_cpu_if = 8; static unsigned int gic_cpu_mask = 0xff; +static unsigned int gich_apr = GICH_APR; +static unsigned int gich_lr = GICH_LR; static inline void writeb_gicd(uint8_t val, unsigned int offset) { @@ -154,9 +156,9 @@ static void gicv2_save_state(struct vcpu *v) * accessed simultaneously by another pCPU. */ for ( i = 0; i < gicv2_info.nr_lrs; i++ ) - v->arch.gic.v2.lr[i] = readl_gich(GICH_LR + i * 4); + v->arch.gic.v2.lr[i] = readl_gich(gich_lr + i * 4); - v->arch.gic.v2.apr = readl_gich(GICH_APR); + v->arch.gic.v2.apr = readl_gich(gich_apr); v->arch.gic.v2.vmcr = readl_gich(GICH_VMCR); /* Disable until next VCPU scheduled */ writel_gich(0, GICH_HCR); @@ -167,9 +169,9 @@ static void gicv2_restore_state(const struct vcpu *v) int i; for ( i = 0; i < gicv2_info.nr_lrs; i++ ) - writel_gich(v->arch.gic.v2.lr[i], GICH_LR + i * 4); + writel_gich(v->arch.gic.v2.lr[i], gich_lr + i * 4); - writel_gich(v->arch.gic.v2.apr, GICH_APR); + writel_gich(v->arch.gic.v2.apr, gich_apr); writel_gich(v->arch.gic.v2.vmcr, GICH_VMCR); writel_gich(GICH_HCR_EN, GICH_HCR); } @@ -182,7 +184,7 @@ static void gicv2_dump_state(const struct vcpu *v) { for ( i = 0; i < gicv2_info.nr_lrs; i++ ) printk(" HW_LR[%d]=%x\n", i, - readl_gich(GICH_LR + i * 4)); + readl_gich(gich_lr + i * 4)); } else { @@ -442,12 +444,12 @@ static void gicv2_update_lr(int lr, const struct pending_irq *p, << GICH_V2_LR_PHYSICAL_SHIFT); } - writel_gich(lr_reg, GICH_LR + lr * 4); + writel_gich(lr_reg, gich_lr + lr * 4); } static void gicv2_clear_lr(int lr) { - writel_gich(0, GICH_LR + lr * 4); + writel_gich(0, gich_lr + lr * 4); } static int gicv2v_setup(struct domain *d) @@ -497,7 +499,7 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) { uint32_t lrv; - lrv = readl_gich(GICH_LR + lr * 4); + lrv = readl_gich(gich_lr + lr * 4); lr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) & GICH_V2_LR_PHYSICAL_MASK; lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; @@ -520,7 +522,7 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) << GICH_V2_LR_HW_SHIFT) | ((uint32_t)(lr_reg->grp & GICH_V2_LR_GRP_MASK) << GICH_V2_LR_GRP_SHIFT) ); - writel_gich(lrv, GICH_LR + lr * 4); + writel_gich(lrv, gich_lr + lr * 4); } static void gicv2_hcr_status(uint32_t flag, bool_t status) @@ -543,7 +545,7 @@ static unsigned int gicv2_read_vmcr_priority(void) static unsigned int gicv2_read_apr(int apr_reg) { - return readl_gich(GICH_APR); + return readl_gich(gich_apr); } static void gicv2_irq_enable(struct irq_desc *desc) @@ -731,6 +733,8 @@ static int __init gicv2_init(struct dt_device_node *node, const void *data) { nr_gic_cpu_if = 16; gic_cpu_mask = 0xffff; + gich_apr = HIP04_GICH_APR; + gich_lr = HIP04_GICH_LR; } res = dt_device_get_address(node, 0, &gicv2.dbase, NULL); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 3d2b3db..804bf24 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -88,6 +88,8 @@ #define GICH_ELSR1 (0x34) #define GICH_APR (0xF0) #define GICH_LR (0x100) +#define HIP04_GICH_APR (0x70) +#define HIP04_GICH_LR (0x80) /* Register bits */ #define GICD_CTL_ENABLE 0x1