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[50.57.142.19]) by mx.google.com with ESMTPS id df5si21205460vdc.100.2014.10.16.07.50.13 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 16 Oct 2014 07:50:14 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XemLz-0002TF-0l; Thu, 16 Oct 2014 14:48:35 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XemLy-0002T1-3o for xen-devel@lists.xensource.com; Thu, 16 Oct 2014 14:48:34 +0000 Received: from [193.109.254.147:3961] by server-13.bemta-14.messagelabs.com id F8/AE-19311-1CADF345; Thu, 16 Oct 2014 14:48:33 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-7.tower-27.messagelabs.com!1413470906!13195141!4 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.12.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3768 invoked from network); 16 Oct 2014 14:48:32 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-7.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 16 Oct 2014 14:48:32 -0000 X-IronPort-AV: E=Sophos;i="5.04,732,1406592000"; d="scan'208";a="181975781" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Thu, 16 Oct 2014 10:48:22 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1XemLh-00040J-3u; Thu, 16 Oct 2014 15:48:17 +0100 From: Stefano Stabellini To: Date: Thu, 16 Oct 2014 15:45:52 +0100 Message-ID: <1413470755-30991-5-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v6 5/8] xen/x86: introduce more cache maintenance operations X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Move the existing flush_page_to_ram flushtlb.h. Signed-off-by: Stefano Stabellini --- Changes in v5: - make order an unsigned int; - add a comment on sub-page granularity support; - cache operations return error; - move the functions to xen/include/asm-x86/flushtlb.h. Changes in v4: - remove _xen in the function names; - implement the functions using existing x86 flushing functions. --- xen/include/asm-x86/flushtlb.h | 16 ++++++++++++++++ xen/include/asm-x86/page.h | 3 --- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/xen/include/asm-x86/flushtlb.h b/xen/include/asm-x86/flushtlb.h index 7f46632..32228e1 100644 --- a/xen/include/asm-x86/flushtlb.h +++ b/xen/include/asm-x86/flushtlb.h @@ -11,6 +11,7 @@ #define __FLUSHTLB_H__ #include +#include #include #include #include @@ -115,4 +116,19 @@ void flush_area_mask(const cpumask_t *, const void *va, unsigned int flags); #define flush_tlb_one_all(v) \ flush_tlb_one_mask(&cpu_online_map, v) +static inline void flush_page_to_ram(unsigned long mfn) {} +static inline int invalidate_dcache_va_range(const void *p, unsigned long size) { return -EOPNOTSUPP; } +static inline int clean_and_invalidate_dcache_va_range(const void *p, unsigned long size) +{ + unsigned int order = get_order_from_bytes(size); + /* sub-page granularity support needs to be added if necessary */ + flush_area_local(p, FLUSH_CACHE|FLUSH_ORDER(order)); + return 0; +} +static inline int clean_dcache_va_range(const void *p, unsigned long size) +{ + clean_and_invalidate_dcache_va_range(p, size); + return 0; +} + #endif /* __FLUSHTLB_H__ */ diff --git a/xen/include/asm-x86/page.h b/xen/include/asm-x86/page.h index 9aa780e..a8bc999 100644 --- a/xen/include/asm-x86/page.h +++ b/xen/include/asm-x86/page.h @@ -344,9 +344,6 @@ static inline uint32_t cacheattr_to_pte_flags(uint32_t cacheattr) return ((cacheattr & 4) << 5) | ((cacheattr & 3) << 3); } -/* No cache maintenance required on x86 architecture. */ -static inline void flush_page_to_ram(unsigned long mfn) {} - /* return true if permission increased */ static inline bool_t perms_strictly_increased(uint32_t old_flags, uint32_t new_flags)