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[50.57.142.19]) by mx.google.com with ESMTPS id l5si21282844vdf.30.2014.10.16.07.50.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 16 Oct 2014 07:50:46 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XemLx-0002Sq-9g; Thu, 16 Oct 2014 14:48:33 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XemLw-0002Sd-3e for xen-devel@lists.xensource.com; Thu, 16 Oct 2014 14:48:32 +0000 Received: from [193.109.254.147:3793] by server-8.bemta-14.messagelabs.com id 03/4F-01875-FBADF345; Thu, 16 Oct 2014 14:48:31 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-7.tower-27.messagelabs.com!1413470906!13195141!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.12.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3546 invoked from network); 16 Oct 2014 14:48:30 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-7.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 16 Oct 2014 14:48:30 -0000 X-IronPort-AV: E=Sophos;i="5.04,732,1406592000"; d="scan'208";a="181975779" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Thu, 16 Oct 2014 10:48:22 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1XemLh-00040J-2D; Thu, 16 Oct 2014 15:48:17 +0100 From: Stefano Stabellini To: Date: Thu, 16 Oct 2014 15:45:51 +0100 Message-ID: <1413470755-30991-4-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v6 4/8] xen/arm: introduce invalidate_dcache_va_range X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Take care of handling non-cacheline aligned addresses and sizes. Signed-off-by: Stefano Stabellini Reviewed-by: Julien Grall Acked-by: Ian Campbell --- Changes in v5: - return int from invalidate_dcache_va_range. Changes in v4: - rename invalidate_xen_dcache_va_range to invalidate_dcache_va_range. --- xen/include/asm-arm/arm32/page.h | 3 +++ xen/include/asm-arm/arm64/page.h | 3 +++ xen/include/asm-arm/page.h | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index 20a6a7f..a07e217 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -19,6 +19,9 @@ static inline void write_pte(lpae_t *p, lpae_t pte) : : "r" (pte.bits), "r" (p) : "memory"); } +/* Inline ASM to invalidate dcache on register R (may be an inline asm operand) */ +#define __invalidate_dcache_one(R) STORE_CP32(R, DCIMVAC) + /* Inline ASM to flush dcache on register R (may be an inline asm operand) */ #define __clean_dcache_one(R) STORE_CP32(R, DCCMVAC) diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 101d7a8..1fd416d 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -14,6 +14,9 @@ static inline void write_pte(lpae_t *p, lpae_t pte) : : "r" (pte.bits), "r" (p) : "memory"); } +/* Inline ASM to invalidate dcache on register R (may be an inline asm operand) */ +#define __invalidate_dcache_one(R) "dc ivac, %" #R ";" + /* Inline ASM to flush dcache on register R (may be an inline asm operand) */ #define __clean_dcache_one(R) "dc cvac, %" #R ";" diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 26c5856..fdcc173 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -268,6 +268,38 @@ extern size_t cacheline_bytes; /* Functions for flushing medium-sized areas. * if 'range' is large enough we might want to use model-specific * full-cache flushes. */ + +static inline int invalidate_dcache_va_range(const void *p, unsigned long size) +{ + size_t off; + const void *end = p + size; + + dsb(sy); /* So the CPU issues all writes to the range */ + + off = (unsigned long)p % cacheline_bytes; + if ( off ) + { + p -= off; + asm volatile (__clean_and_invalidate_dcache_one(0) : : "r" (p)); + p += cacheline_bytes; + size -= cacheline_bytes - off; + } + off = (unsigned long)end % cacheline_bytes; + if ( off ) + { + end -= off; + size -= off; + asm volatile (__clean_and_invalidate_dcache_one(0) : : "r" (end)); + } + + for ( ; p < end; p += cacheline_bytes ) + asm volatile (__invalidate_dcache_one(0) : : "r" (p)); + + dsb(sy); /* So we know the flushes happen before continuing */ + + return 0; +} + static inline int clean_dcache_va_range(const void *p, unsigned long size) { const void *end;