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[50.57.142.19]) by mx.google.com with ESMTPS id cz3si12530759vcb.103.2014.10.13.08.03.11 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 13 Oct 2014 08:03:12 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Xdh7p-0004L9-Cd; Mon, 13 Oct 2014 15:01:29 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Xdh7m-0004H8-O2 for xen-devel@lists.xensource.com; Mon, 13 Oct 2014 15:01:26 +0000 Received: from [193.109.254.147:6419] by server-11.bemta-14.messagelabs.com id 68/7C-14213-649EB345; Mon, 13 Oct 2014 15:01:26 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-16.tower-27.messagelabs.com!1413212483!7049834!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.12.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 20082 invoked from network); 13 Oct 2014 15:01:24 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-16.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 13 Oct 2014 15:01:24 -0000 X-IronPort-AV: E=Sophos;i="5.04,711,1406592000"; d="scan'208";a="180809047" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Mon, 13 Oct 2014 11:01:09 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1Xdh7P-0008Ho-NO; Mon, 13 Oct 2014 16:01:03 +0100 From: Stefano Stabellini To: Date: Mon, 13 Oct 2014 15:58:39 +0100 Message-ID: <1413212324-664-3-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v5 3/8] xen/arm: return int from flush_page_to_ram and *_dcache_va_range X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: These functions cannot really fail on ARM, but their x86 equivalents can (-EOPNOTSUPP). Change the prototype to return int. Signed-off-by: Stefano Stabellini --- xen/arch/arm/mm.c | 6 ++++-- xen/include/asm-arm/page.h | 8 +++++--- xen/include/asm-x86/page.h | 3 ++- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 996687b..f6f20aa 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -377,12 +377,14 @@ unsigned long domain_page_map_to_mfn(const void *ptr) } #endif -void flush_page_to_ram(unsigned long mfn) +int flush_page_to_ram(unsigned long mfn) { + int ret; void *v = map_domain_page(mfn); - clean_and_invalidate_dcache_va_range(v, PAGE_SIZE); + ret = clean_and_invalidate_dcache_va_range(v, PAGE_SIZE); unmap_domain_page(v); + return ret; } void __init arch_init_memory(void) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 1327b00..6265c45 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -268,16 +268,17 @@ extern size_t cacheline_bytes; /* Functions for flushing medium-sized areas. * if 'range' is large enough we might want to use model-specific * full-cache flushes. */ -static inline void clean_dcache_va_range(const void *p, unsigned long size) +static inline int clean_dcache_va_range(const void *p, unsigned long size) { const void *end; dsb(sy); /* So the CPU issues all writes to the range */ for ( end = p + size; p < end; p += cacheline_bytes ) asm volatile (__clean_dcache_one(0) : : "r" (p)); dsb(sy); /* So we know the flushes happen before continuing */ + return 0; } -static inline void clean_and_invalidate_dcache_va_range +static inline int clean_and_invalidate_dcache_va_range (const void *p, unsigned long size) { const void *end; @@ -285,6 +286,7 @@ static inline void clean_and_invalidate_dcache_va_range for ( end = p + size; p < end; p += cacheline_bytes ) asm volatile (__clean_and_invalidate_dcache_one(0) : : "r" (p)); dsb(sy); /* So we know the flushes happen before continuing */ + return 0; } /* Macros for flushing a single small item. The predicate is always @@ -353,7 +355,7 @@ static inline void flush_xen_data_tlb_range_va(unsigned long va, } /* Flush the dcache for an entire page. */ -void flush_page_to_ram(unsigned long mfn); +int flush_page_to_ram(unsigned long mfn); /* * Print a walk of a page table or p2m diff --git a/xen/include/asm-x86/page.h b/xen/include/asm-x86/page.h index 9aa780e..006e3fa 100644 --- a/xen/include/asm-x86/page.h +++ b/xen/include/asm-x86/page.h @@ -21,6 +21,7 @@ #endif #include +#include /* Read a pte atomically from memory. */ #define l1e_read_atomic(l1ep) \ @@ -345,7 +346,7 @@ static inline uint32_t cacheattr_to_pte_flags(uint32_t cacheattr) } /* No cache maintenance required on x86 architecture. */ -static inline void flush_page_to_ram(unsigned long mfn) {} +static inline int flush_page_to_ram(unsigned long mfn) { return -EOPNOTSUPP; } /* return true if permission increased */ static inline bool_t