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[50.57.142.19]) by mx.google.com with ESMTPS id gu5si5658803vdb.90.2014.09.24.07.19.23 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 24 Sep 2014 07:19:23 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XWnNp-0000CE-5A; Wed, 24 Sep 2014 14:17:29 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XWnNo-0000C3-3I for xen-devel@lists.xen.org; Wed, 24 Sep 2014 14:17:28 +0000 Received: from [85.158.139.211:24331] by server-8.bemta-5.messagelabs.com id 6A/08-22440-772D2245; Wed, 24 Sep 2014 14:17:27 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-14.tower-206.messagelabs.com!1411568245!6398304!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 6.12.2; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3694 invoked from network); 24 Sep 2014 14:17:26 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-14.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 24 Sep 2014 14:17:26 -0000 X-IronPort-AV: E=Sophos;i="5.04,589,1406592000"; d="scan'208";a="175716926" Message-ID: <1411568192.28127.40.camel@kazak.uk.xensource.com> From: Ian Campbell To: Suriyan Ramasami Date: Wed, 24 Sep 2014 15:16:32 +0100 In-Reply-To: References: <1411561579.28127.26.camel@kazak.uk.xensource.com> Organization: Citrix Systems, Inc. X-Mailer: Evolution 3.12.2-1+b1 MIME-Version: 1.0 X-DLP: MIA1 Cc: "xen-devel@lists.xen.org" Subject: Re: [Xen-devel] xen:arm boot failures after commit 1c92a2aa* X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.177 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On Wed, 2014-09-24 at 05:36 -0700, Suriyan Ramasami wrote: Thanks, > (XEN) VTCR_EL2: 80003518 THis has changed from 0x80003558 before this change (sorry, this was in your original report too and I failed to spot it). The missing bit changes the starting level of the PT from L1 to L2, which ain't gonna work very well ;-). I can't for the life of me figure out how/why this works on arndale, but it does... Anyway, does this fix it for you? 8<------------------ >From ada27d3a56ba89513721e24abe4a4bebee2ab9cf Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Wed, 24 Sep 2014 15:13:28 +0100 Subject: [PATCH] xen: arm: correct VTCR setting on arm32. 1c92a2aaf8c6 "xen: arm: support for up to 48-bit IPA addressing on arm64" inadvertently changes the VTCR setting for 32-bit from 0x80003558 to 0x80003518, changing the SL0 setting from 0x1 (p2m starts at L1) to 0x0 (p2m starts at L2). For some (inexplicable) reason this doesn't cause any issue on Arndale but it does on the OdroidXU. Reported-by: Suriyan Ramasami Signed-off-by: Ian Campbell Reviewed-by: Julien Grall --- xen/arch/arm/p2m.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 4dccf7b..70929fc 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1163,6 +1163,7 @@ void __init setup_virt_paging(void) #ifdef CONFIG_ARM_32 printk("P2M: 40-bit IPA\n"); val |= VTCR_T0SZ(0x18); /* 40 bit IPA */ + val |= VTCR_SL0(0x1); /* P2M starts at first level */ #else /* CONFIG_ARM_64 */ const struct { unsigned int pabits; /* Physical Address Size */